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The Principal High-Speed I/O Architect designs interconnect architectures for SoCs, collaborating on performance and efficiency in various markets.

As a Performance Analysis Engineer, you will analyze SoC performance, identify bottlenecks, collaborate with architects, and develop testing workflows.

Architect and design high-volume SoC platforms using Arm IP across mobile, automotive, datacenter, networking and IoT. Lead cross-functional teams to define platform architecture, optimize performance and power, coordinate IP delivery, drive partner engagements, and influence roadmap and feature development. Guide specification maturity and ensure on-time delivery while driving innovation and continuous improvement.

The Senior Director will lead Cloud AI Platform Solutions, managing customer engagement, platform readiness, team leadership, and cross-functional alignment to drive successful server-class SoC platform deployments.

The SoC RAS Architect drives reliability and serviceability strategies for SoCs, ensuring compliance with data center standards through collaboration with design and engineering teams.

The Director of Strategic Sales leads business development and partnerships across Cloud AI and Datacenter accounts, focusing on strategic sales growth and ecosystem collaboration.

The HPC Engineer will operate and enhance Arm's HPC platforms, focusing on reliability, automation, and user experience while collaborating with engineering and infrastructure teams.

The role involves developing ML methods for robotics, focusing on integration with learning-based planning and control under real-world constraints. Responsibilities include benchmarking approaches and contributing to system prototypes.

The role involves developing perception systems for robotics, integrating them with planning and control systems, and evaluating performance under constraints.

The role involves developing real-time control algorithms and safety mechanisms for robotic systems, integrating them with learning-based components, and ensuring system compatibility under strict latency constraints.