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Join Arm's ML Hardware Architecture team to accelerate ML across next-gen Arm IP. Develop and analyze functional and performance models, characterize workloads, perform performance analysis, and build automation and visualization tools for modeling results.

Lead system-level product engineering for SoC/CPU/GPU silicon from pre-silicon readiness through post-silicon bring-up. Own manufacturability and SLT manufacturing flow, drive yield improvement, characterization, system-level qualification, failure debug, VF margin validation, and cross-functional coordination with design, packaging, validation, test, software, and partners.

Design and build ML DevOps infrastructure and end-to-end pipelines to deploy data, models, and software for Edge AI applications. Implement secure repository and CI/CD/CT practices, collaborate with cross-functional teams, and define metrics and monitoring to ensure delivery and operational performance.

Lead cross-functional engineering teams to plan, schedule, track, and deliver System IP and SoC-related products (CPU, GPU, MMU, GIC, PHY, interconnect). Manage resources, budgets, risks, changes, and dependencies; communicate with product and technical leads; ensure on-spec, high-quality, and timely delivery across the hardware/Soft IP development lifecycle.

Support deployment, training, and support of internal SoC design and verification flows. Work with project engineers and methodology developers to ensure front-end and back-end flows function correctly, ramp teams, liaise with EDA vendors to resolve tooling issues, and identify efficiency improvements across engineering projects.

Lead cross-functional product engineering for SoC/CPU/GPU manufacturability from pre-silicon readiness through post-silicon bring-up. Own manufacturing flow, ATE/SLT test and correlation, yield improvement, silicon/package reliability qualification, PVTF characterization, and failure analysis while coordinating with foundries, OSATs, design, validation, test, and quality. Support NPI/HVM readiness and audits, with international travel up to 20%.

Lead subsystem-level verification of PCIe and CXL IOs: define verification strategy, craft test plans, develop SystemVerilog/Verilog/UVM testbenches, run simulation/emulation, debug issues, improve methodologies, and mentor junior engineers while coordinating with architects and project managers.

Lead response to high‑priority security incidents, coordinate investigations with internal teams, providers and law enforcement, improve IR and forensics capabilities across Windows, Linux, Mac, network and cloud environments, run post‑incident reviews and root cause analysis, contribute to IR policies and detection tuning, and support readiness exercises and incident planning.

The role involves supporting the delivery of soft IP, optimizing designs, ensuring partner success, and developing methodologies for implementation analysis.

Develop and support methodologies for 3DIC and 2.5D physical design, focusing on timing, power, thermal, and multiphysics analysis with cross-team collaboration.