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Design and verification engineer for Arm’s next-generation network-on-chip interconnect products. Responsibilities include specifying, creating, and debugging SystemVerilog/UVM constrained-random testbenches; verifying multiprocessing microarchitectures, cache coherence, and AMBA protocols; applying software engineering, scripting, and formal verification skills to ensure reliable, high-performance silicon IP.

Design and verify hardware security IP and embedded processor subsystems for SoCs. Develop test plans, UVM/SystemVerilog/Verilog and C testbenches, verification models, and test strategies. Debug failures, ensure functional coverage, and support power and performance optimization. Work with design and project management teams, improve verification methodologies, and mentor engineers. Focus areas include cryptography, key management, secure boot, hardware roots of trust, ARM architectures, multi-clock and multi-power domains, and firmware/hardware co-verification.

Develop and execute system-level post-silicon validation, stress workloads, and characterization tests for Arm SoC processors. Debug and resolve silicon and system issues using hardware instrumentation and software tools. Create test plans, correlate validation results with manufacturing tests, and collaborate with engineering teams to improve validation practices. Requires pre- and post-silicon validation experience, software development skills in C/C++, ARM assembly, Python, and scripting, plus a technical degree or equivalent experience.

Own end-to-end ASIC physical implementation from RTL through GDSII and tapeout for complex CPU, GPU, interconnect, and SoC designs. Drive timing, power, physical, and signoff closure across MCMM scenarios; collaborate with architecture, RTL, DFT, EDA vendors, and foundries; resolve implementation issues; and improve automation, methodologies, and flows for geographically distributed teams.

This role focuses on enhancing developer experience through improved tools and solutions, collaborating with developers and engineering teams, and managing product roadmaps for performance tooling.

Coordinate third-party IP delivery and lifecycle management across semiconductor programs. Track vendor commitments, procurement readiness, schedules, risks, dependencies, and recovery plans. Partner with engineering, procurement, quality, legal, finance, program management, and suppliers to resolve blockers and support leadership reporting. Improve IP lifecycle processes, reporting tools, and workflows while ensuring delivery and compliance readiness.

Own the product direction for Physical AI applications and the reusable ML and software stack running on Arm-based silicon. Define target workloads, requirements, interfaces, roadmaps, benchmarks, acceptance criteria, and release decisions across robotics, autonomy, AI inference, middleware, tooling, simulation, and deployment. Validate customer and partner needs, guide build-versus-partner choices, evaluate measured prototypes, and align engineering, architecture, product, and business leaders through delivery and launch.

Leads global sourcing strategy for semiconductor foundry and ASIC services from product development through high-volume manufacturing. Manages foundry and ASIC supplier relationships, negotiations, capacity reservations, pricing, NRE, masks, and long-term agreements. Builds semiconductor cost models, secures advanced-node capacity, mitigates supply and technology risks, monitors market dynamics, and presents sourcing recommendations to senior leadership. Partners cross-functionally with engineering, product, operations, finance, and supply chain teams.

Designs and optimizes board-level power architectures for high-performance Arm compute platforms, including DC-DC converters, VRMs, PMICs, power trees, and power delivery networks. Responsibilities include simulation, PCB schematic and layout review, power integrity analysis, laboratory validation, dynamic load testing, EMI/EMC mitigation, thermal collaboration, customer design-in support, and technical documentation. The role collaborates with SoC architects, suppliers, and multidisciplinary engineering teams.

Leads global sourcing strategy for semiconductor IC test equipment, hardware, and outsourced test services. Manages ATE platforms, OSAT relationships, supplier negotiations, test capacity planning, equipment deployment, capital investments, utilization, and lifecycle management. Partners with engineering and operations teams to support product development, qualification, ramp, and high-volume manufacturing while presenting sourcing strategies, costs, risks, and capacity plans to senior leadership.