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Drive strategic account growth by developing executive relationships, leading IP licensing engagements, and coordinating cross-functional teams. Manage full customer lifecycle, maintain pipeline and forecasts, negotiate complex agreements, and expand Arm's footprint within semiconductor and technology customers.

Lead supply planning for a fabless semiconductor company: develop and implement supply planning processes, manage supplier forecasts and capacity, lock in fab capacity, oversee materials to finished goods, and build supplier relationships to balance on-time delivery and costs across product lifecycles.

Lead strategy and execution for a next-generation AI inference platform: define roadmap, drive inference architecture and orchestration, enable hardware-software co-design, own control plane services and KPIs, and align cross-functional teams to improve latency, throughput, and cost efficiency.

Design RTL logic for a coherent interconnect fabric using SystemVerilog. Collaborate with verification, implementation, performance, and power teams to deliver high-performance, low-power IP. Track and coordinate tasks, debug functional and performance issues with simulation and tools, and improve design methodology across the System IP group.

Lead architecture, design, and delivery of coherent and non-coherent SoC interconnect fabrics. Define topology, QoS, latency, bandwidth, and power strategies; drive performance modeling, RTL microarchitecture and verification, debug system-level issues, mentor engineers, and plan interconnect roadmaps while collaborating with CPU/GPU/NPU/memory teams.

The role involves field applications engineering focused on silicon, likely supporting customers and assisting in technical implementations.

Lead and manage a global team of Silicon FAEs, ensure customer satisfaction from evaluation to deployment, establish operational frameworks and metrics, and engage with executives on strategic accounts.

As a GRC Risk Manager, you will lead security risk assessments, manage supply chain cyber risks, and partner across departments to ensure effective risk management.

Lead platform software and ecosystem enablement for Arm technologies, translating partner needs into software requirements and validation plans. Drive readiness across firmware, OS (Android, Linux, Windows), tooling, and reference platforms (simulation, emulation, FPGA, testchip). Coordinate cross-functional teams, prioritize features, represent software readiness to senior leadership and partners, and build a team to scale platform and firmware enablement.

Lead sub-system level verification of high-speed IOs (PCIe/CXL) including test plan creation, SystemVerilog/Verilog/UVM testbench and test development, simulation and emulation, performance and interoperability verification, debugging failures, improving verification methodology, and mentoring junior engineers while collaborating with architects, RTL designers, and cross-functional teams.