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The Senior Analog IP Design Engineer will be responsible for developing and customizing analog IP blocks and subsystems, participating in spec definition, and collaborating with teams to meet customer requirements. This role requires knowledge in CMOS IC development process, High Speed SerDes, ADC, DAC, PLL, and more. The candidate should have 2 years of relevant experience and be able to work independently and with global teams.
As a Principal Software Engineer at Cadence, you will work on challenging projects involving state-of-art design IPs. Responsibilities include driver development, model development, virtual prototyping, testing, and end customer support on software drivers and applications. Requirements include relevant experience, software architecture and programming skills, understanding of microcontrollers and system-on-chip architecture, and proficiency in various technologies and tools. Beneficial skills include familiarity with ISO standards, coding guidelines, and software development processes.
The Principal Software Engineer will develop new applications for machine learning, work with large databases, develop algorithms, and solve complex problems in the IC implementation flow. Responsibilities include scheduling, software designing, debugging, and developing AI-enabled synthesis and implementation tools.
The Lead Software Engineer at Cadence is responsible for designing, implementing, and validating algorithms for the UFE platform, as well as providing R&D support for application and product engineers. This role involves debugging, problem analysis, and introducing new features to enhance the platform.
The Technical Marketing Manager at Cadence is responsible for executing marketing programs for hardware-assisted verification and virtual platforms. This role involves product management collaboration, technical sales training, competitive analysis, and creating marketing collateral while interacting with customers and cross-functional teams to align on product features and market trends.
The Lead Software Engineer will develop business logic components for a hardware verification tool using C++ and Java. Responsibilities include ensuring performance and scalability, collaborating with global teams, and working in an Agile environment.
The Principal Solutions Engineer at Cadence will develop high-performance PERC decks. This role requires collaborating with customers and internal teams while focusing on advanced node PERC solutions. The position emphasizes programming and scripting in various languages and requires a solid background in Physical Design and Verification.
The Lead Product Engineer will trace customer requirements and deliver high-quality solutions, support product development using the Innovus tool, and validate advanced features while participating in customer meetings for advanced semiconductor technologies.
Cadence Design Systems is seeking a Principal Software Engineer to work on the Genus Synthesis Solution product, focusing on synthesis optimization algorithms for timing, area, and power design metrics. Responsibilities include algorithm design, validation, R&D support, and mentoring. Candidates must have 7-12 years of experience with strong C/C++ proficiency, UNIX/LINUX familiarity, RTL knowledge, and experience in language compiler and timing analysis projects.
The Lead Verification Engineer at Cadence is responsible for leading design verification projects, managing the entire process from concept to closure, and developing functional verification environments. A strong background in System Verilog and UVM is essential, along with experience in IP verification, particularly in memory IP.
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