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The role involves working on Celerity AI Solution related to various simulations, contributing to AI projects, preferably with a PhD and engineering background.

This role involves designing, developing, and maintaining PCIe/CXL AVIP/VB components, focusing on protocol functionality and performance, while collaborating with teams and supporting customers.

The Lead Digital Verification Engineer is responsible for verifying digital RTL and developing reusable verification components, contributing to all aspects of digital verification, and working with design teams.