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Provide pre- and post-sales technical consulting for MSC Marc nonlinear simulations: deliver demos, POCs, training, troubleshooting, project implementation, and develop best-practice documentation for industries like batteries, automotive, composites, and electronics packaging.

Design and automate high-fidelity validation strategies and benchmark models for advanced nonlinear FEA solvers. Build repeatable test cases, validate solver behavior, collaborate with developers and QA, and produce evidence-based validation reports to improve CAE product quality.

Design and develop digital flow using Innovus, collaborate with R&D on technical specifications, work with production validation to ensure quality releases, provide technical support and training to Cadence AP business, and collaborate with global cross-functional teams for customer engagement.

Administer and support Coupa/S2P procurement platforms for India, APAC and Australia. Lead upgrades, deployments, SIT/UAT testing, incident resolution, configuration, workflows, and documentation. Provide stakeholder support, training, user guidance, and continuous improvement to enhance system performance and automation.

Serve as the primary technical consultant for Simufact manufacturing simulation solutions: engage customers, deliver demos/POCs, implement projects, create models, run FEA simulations, interpret results, provide training, and support sales and product improvement across forming, welding, and additive processes.

Serve as primary technical consultant for MSC Nastran solutions across customer lifecycle: engage customers, deliver demos/POCs, validate solutions, implement projects, train users, provide day-to-day model setup and solver support, troubleshoot structural and multiphysics simulations, and develop technical documentation and use cases.

Design, develop, verify and deploy Verification IP (VIP). Build test environments using SystemVerilog/UVM, debug, and implement protocol-layer functionality (UCIe, PCIe, CXL, Ethernet). Collaborate cross-functionally and with customers; use C/C++ and scripting to support verification tasks.

The Lead Software Engineer at Cadence develops software focusing on industry protocols and design implementations, while fostering a collaborative team culture.

The Principal Design Engineer will be responsible for the design verification of IPs, including developing UVM testbenches and formal verification.

The Principal Software Engineer will create CXL and PCIe switches, requiring expertise in C++, HDL, and knowledge of relevant protocols.