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Develop and optimize advanced EDA software within the Virtuoso Heterogeneous Integration toolset. Design, debug, and scale EM/thermal/RC extraction and multi‑physics features, improve runtime and CPU/GPU utilization, apply ML/AI to automate workflows, and mentor junior engineers while delivering customer-focused solutions.

The role involves analyzing business performance, enhancing analytical models, translating technical concepts, automating reporting, and collaborating across teams to provide insights to leadership.

The Lead Design Engineer ensures the functionality of complex CPU cores through DV architecture, defines methodologies, architects verification infrastructures, and mentors teams across a global context.

Customer-facing pre-sales engineer driving Palladium hardware emulation evaluations, demos, and benchmarks; enable customer adoption, optimize verification flows, provide hands-on support, and feed product insights to R&D and marketing.

Design and implement custom analog/mixed-signal IC layout floorplans, matching guides, component placement, and high-speed PHY routing (SerDes, USB, DDR). Perform DRC/LVS/ERC and EMIR/Voltus-FI analyses, collaborate with analog circuit and digital P&R teams, and optimize layouts for noise, coupling, and manufacturability.

Lead product strategy, roadmap, and go-to-market for a custom and analog design product line. Engage senior analog designers, define requirements and pricing, drive adoption and revenue, align R&D/sales/marketing, hire and coach product managers, and track success metrics for adoption, productivity impact, pipeline, and revenue.

Lead development, automation, and maintenance of physical implementation EDA flows; optimize PPA and TFM for IP/SoC in advanced nodes; manage regression infrastructure; perform digital implementation using Cadence tools; automate full-chip floorplanning with AI; collaborate across teams and lead design efforts.

Provide customer support for analog, mixed-signal, and RF design flows using Cadence tools (Virtuoso, Spectre family). Debug circuit and simulation issues, apply best practices in schematic-driven layout and simulation setup, create technical documentation and automation, collaborate with R&D and field teams, and mentor junior engineers.

Provide technical support and demonstrations for digital IC implementation. Lead full APR flow activities (floorplan, placement, timing analysis, CTS, signoff timing, PV closure), support customer engagements and tape-out efforts, mentor team members, and use scripting (shell/Perl/Tcl). Cadence Innovus experience and advanced-node tape-out knowledge are a plus. Strong English/Chinese communication and self-motivation required.

Provide technical support to customers using digital/physical design flows: debug issues, improve productivity, produce knowledge content and scripts, and liaise with R&D to deliver solutions for synthesis and digital implementation.