The Role
Lead development, automation, and maintenance of physical implementation EDA flows; optimize PPA and TFM for IP/SoC in advanced nodes; manage regression infrastructure; perform digital implementation using Cadence tools; automate full-chip floorplanning with AI; collaborate across teams and lead design efforts.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
- Development, automation and maintenance of EDA flows and scripts for physical implementation
- Develop TFM to optimize PPA for IP’s and Soft Controllers
- PPA characterization and optimization of flow for performance-oriented and power-oriented best-in-class IP cores in advanced process nodes, on TSMC, Intel, Samsung and Rapidus Foundries
- Manage regression infrastructure that tracks quality of the RTL/flow development as well as the PPA of the key designs.
- Digital design implementation using Cadence EDA tools - Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus and other backend tools
- Candidate will be working on automation of Full chip floorplanning using latest AI tools. Involving in active AI agent based partition for Full Chip Floorplanning.
- Required skills –
- Educational Qualification: MS/MTech/BE/ BTech in Electronics from reputed institutes with 5 + years' experience
- Physical design experience in ASIC design environment
- Should have knowledge of complete ASIC Design Flow, including Synthesis, Physical Designing , Timing Analysis, Power Analysis and Formal Verification
- Should have excellent leadership, communication, analytical and problem solving skills.
- Expertise on High frequency design methodologies for complete ASIC backend flows.
- Candidate with experience in Full Chip (SoC level) floorplanning, pin assignment, global clock distribution across all subsystems is a plus point.
- Good communication skills, strong analytical problem solving skills and willingness to learn quickly.
- Solid scripting skills including Python and Tcl.
- Should be self-motivated and good team player.
Skills Required
- MS/MTech/BE/BTech in Electronics with 5+ years' experience
- Physical design experience in an ASIC design environment
- Knowledge of complete ASIC design flow including synthesis, physical design, timing analysis, power analysis, and formal verification
- Expertise in high-frequency design methodologies for complete ASIC backend flows
- Solid scripting skills including Python and Tcl
- Excellent leadership, communication, analytical and problem solving skills
- Experience with full-chip (SoC level) floorplanning, pin assignment, and global clock distribution across subsystems
- Self-motivated and strong team player
Cadence Design Systems Compensation & Benefits Highlights
The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.
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Equity Value & Accessibility — A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
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Healthcare Strength — Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
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Leave & Time Off Breadth — Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.
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The Company
What We Do
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.
