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16 Hours Ago
Bangalore, Bengaluru Urban, Karnataka, IND
8,216 Employees
Mid level
8,216 Employees
Mid level
Cloud • Hardware • Software • Semiconductor
The Lead Design Engineer will perform pre and post silicon Physical Layer Electrical Validation on High Speed SERDES IP. Responsibilities include designing hardware/software infrastructure, implementing rigorous test suites, debugging silicon issues, and generating test reports.
16 Hours Ago
Bangalore, Bengaluru Urban, Karnataka, IND
8,216 Employees
Senior level
8,216 Employees
Senior level
Cloud • Hardware • Software • Semiconductor
As a Principal Design Engineer at Cadence, you will lead the design of Analog Mixed Signal (AMS) for High-speed Memory PHYs. You will oversee subsystems, mentor team members, participate in technical discussions, and ensure quality and efficiency in AMS design.
16 Hours Ago
Zhubei City, Hsinchu County, TWN
8,216 Employees
Senior level
8,216 Employees
Senior level
Cloud • Hardware • Software • Semiconductor
The Principal Application Engineer will provide technical support in digital IC design implementation, demonstrate full APR flow capabilities, assist in customer engagements, and lead team members effectively with minimal instruction. Key experience in advanced node design and design tape-out is required.
8,216 Employees
Expert/Leader
Cloud • Hardware • Software • Semiconductor
Cadence is seeking a Sr. Principal Software Engineer to work on the design, development, and verification of verification IP tools. The candidate should have strong communication skills, domain experience, and proficiency in functional verification using SV/UVM.
16 Hours Ago
Bangalore, Bengaluru Urban, Karnataka, IND
8,216 Employees
Entry level
8,216 Employees
Entry level
Cloud • Hardware • Software • Semiconductor
As a Lead Support Application Engineer at Cadence in Bangalore/Noida, you will provide technical support for IC level Power System analysis products, work closely with customers to debug complex issues, and guide them with implementing software in their design methodologies. You will have opportunities for technical knowledge acquisition, exposure to industry design practices, and contribute to key technology solutions. Join a diverse team passionate about innovation and technology.
16 Hours Ago
Bangalore, Bengaluru Urban, Karnataka, IND
8,216 Employees
Entry level
8,216 Employees
Entry level
Cloud • Hardware • Software • Semiconductor
As a Principal Application Engineer at Cadence, you will provide technical consultation for digital & sign-off domain products to worldwide customers, debug complex issues, guide implementation of software, and contribute to product improvement initiatives.
16 Hours Ago
Edinburgh, Midlothian, Scotland, GBR
8,216 Employees
Entry level
8,216 Employees
Entry level
Cloud • Hardware • Software • Semiconductor
The Digital Design Engineer I will work in Cork as part of an experienced Controller IP Team. Responsibilities include Verilog RTL Design, Metric Driven Verification, and using Front-end design tools.
16 Hours Ago
Bangalore, Bengaluru Urban, Karnataka, IND
8,216 Employees
Expert/Leader
8,216 Employees
Expert/Leader
Cloud • Hardware • Software • Semiconductor
Cadence is hiring a Memory Design Engineer with 15-25 years of experience to work in their Memory IP team in Hyderabad. The responsibilities include circuit design, simulation, verification, and silicon bring-up for memory design blocks. Proficiency in Cadence, Mentor Graphics, and Synopsys tools is required, along with good technical communication and teamwork skills.
16 Hours Ago
Bangalore, Bengaluru Urban, Karnataka, IND
8,216 Employees
Senior level
8,216 Employees
Senior level
Cloud • Hardware • Software • Semiconductor
Work with the Cadence global IC design team to develop semiconductor IP for top electronic product companies, ensuring continuous quality improvement and adherence to quality procedures.
16 Hours Ago
Bangalore, Bengaluru Urban, Karnataka, IND
8,216 Employees
Mid level
8,216 Employees
Mid level
Cloud • Hardware • Software • Semiconductor
Lead Design Engineer responsible for creating and maintaining functional verification environments, defining verification strategies, and collaborating with cross-functional teams. Requires expertise in Verilog, SystemVerilog, UVM methodology, RTL, and various verification domain skills. Desirable skills include power-aware RTL, formal verification, gate-level simulations, and exposure to automotive IP verification.
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