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The Lead Software Engineer at Cadence will enhance software development for the Protium P&R tool, focusing on improving quality of results (QoR) and performance timing while collaborating with users to deploy new features. Candidates must have a strong background in software development and CS fundamentals.

The Principal Software Engineer at Cadence will leverage strong CS fundamentals to improve the quality of results (QoR) of the Protium Place & Route (P&R) tool. Responsibilities include enhancing P&R features for improved performance and collaborating with users to deploy tools effectively.

The Lead Solutions Engineer will review design specifications, develop verification strategies and test plans, and create constrained random verification environments. Responsibilities include writing functional tests and assertions to meet verification goals, with a focus on SOC verification using C-based test cases and various protocols.

The Lead Design Engineer at Cadence will develop firmware for various memory interfaces, collaborate with hardware designers and architects, deduce co-verification plans with the verification team, and support debugging efforts on simulations and silicon boards.

The Principal Design Engineer at Cadence is responsible for leading design verification projects, confirming complex designs are verified from concept to closure. This role requires extensive experience in functional verification fundamentals, test plan generation, and environment development using System Verilog and UVM.

The Principal Design Engineer is responsible for the integration, customization, and post-silicon bring-up of CDNS DDR IP subsystems. This role involves resolving complex implementation issues, supporting integration reviews, performing simulations for functionality, and enhancing customer communication and experience.

The Principal Design Engineer at Cadence will lead development in custom accelerator SoCs and collaborate with computational simulation teams. Responsibilities include designing verification processes, creating and maintaining test-benches, and participating in IP delivery and SoC tape-out. Candidates must have robust debugging skills and experience in a cross-team environment.