Principal Application Engineer

Reposted 24 Days Ago
Be an Early Applicant
Shanghai, Shanghai Municipality, Shanghai, CHN
In-Office
Mid level
Artificial Intelligence • Cloud • Hardware • Software • Semiconductor
The Role
The Principal Application Engineer will implement physical design, engage in floor planning, power grid design, and collaborate with design teams for successful tapeouts.
Summary Generated by Built In
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
  • The candidate will perform the physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
  • The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed designs at the latest technology nodes.
  • The responsibility of the candidate includes participating in or leading next generation physical design, methodology and flow development.
  • The candidate will work closely with RTL design team to ensure successful tapeouts.

 

Requirement:

  • BS/MS in EE/CS with 3+ years of hands-on experience in physical design and verification.
  • Experienced with ASIC design flow, hierarchical physical design strategies, methodologies, and understand deep sub-micron technology issues.
  • Solid knowledge on Low Power Design, DFT, static timing analysis and closure, data skew balancing, duty cycle adjustment, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM and P&R.
  • Able to assume responsibility for a variety of technical tasks and to work independently
  • Able to be hands-on at all levels of design, with the ability to verify, test, and characterize own designs
  • Self-motivated, able to work as a team player, and good English communication skills

 

We’re doing work that matters. Help us solve what others can’t.

Skills Required

  • BS/MS in EE/CS
  • 3+ years of hands-on experience in physical design and verification
  • Experienced with ASIC design flow
  • Solid knowledge on Low Power Design and physical verification
  • Good English communication skills

Cadence Design Systems Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Cadence Design Systems and has not been reviewed or approved by Cadence Design Systems.

  • Equity Value & Accessibility A discounted ESPP with a lookback feature and equity included in total compensation make ownership broadly accessible and potentially meaningful. Structured compensation at an industry leader adds predictability to equity participation.
  • Healthcare Strength Medical, dental, and vision coverage are described as solid, with mental‑health/EAP and fertility support enhancing the offering. The breadth across core care and family‑building needs strengthens the healthcare package.
  • Leave & Time Off Breadth Global Recharge Days, volunteer time off, and companywide breaks indicate a comprehensive time‑off framework. In addition, many salaried roles are described as having flexible or generous PTO policies.

Cadence Design Systems Insights

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The Company
HQ: San Jose, CA
8,216 Employees
Year Founded: 1988

What We Do

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and IP are used by customers to deliver products to market faster. The company's Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud, data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For.

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