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Lead digital design engineer responsible for designing and integrating SoC IPs, developing microarchitectural specifications, performing lint, CDC, synthesis, and PPA optimization, and supporting verification and physical design teams. The role also involves creating synthesis constraints, debugging design issues, automating repetitive tasks with scripting, and collaborating across engineering teams.

Design and integrate SoC IPs from architectural specifications; perform Lint and CDC checks; develop synthesis constraints and optimize power, performance, and area. Create microarchitectural specifications, support verification and physical design teams, and automate repetitive tasks using scripting. Collaborate across teams to execute projects effectively.

Develop and deploy Verification IP through functional verification, SystemVerilog/UVM test environment creation, debugging, and protocol validation. The role requires expertise with UCIe, PCIe, CXL, Ethernet, and UALink, plus C/C++ and scripting skills. Responsibilities include collaborating cross-functionally, adapting to new technologies, supporting customers, and applying strong digital electronics, programming, analytical, and communication fundamentals.

Analyze customer requirements and emulation performance across complex SoC verification environments. Investigate customer issues, identify bottlenecks, analyze performance trends, run experiments, and improve compile and runtime performance. Gather and publish metrics, benchmark and validate product flows, create technical collateral, and collaborate with Product Engineering, R&D, Product Validation, and Customer Success teams to deliver product enhancements.

Develop runtime software for the Palladium emulation system, troubleshoot software issues, and collaborate with software and hardware engineers on product development. The role requires strong C and C++ programming, object-oriented design, Linux experience, source-code control proficiency with Perforce and Git, analytical problem-solving ability, and effective English communication. Multithreading experience is advantageous.

Develop and maintain the Palladium synthesizer, implement VHDL and Verilog feature support, and improve logic optimization and performance. The role requires software development in C/C++, operating systems knowledge, RTL modeling with Verilog/SystemVerilog, VHDL, or SystemC, and collaboration across multi-site teams. Experience with RTL bus functional models, UVM, SC/TLM, EDA tool development, logic design verification, or AI coding tools is advantageous.

Develop and maintain the Palladium synthesizer, implement VHDL and Verilog feature support, and optimize logic and performance. The role requires C/C++ proficiency, operating systems knowledge, and experience with Verilog/SystemVerilog, VHDL, or SystemC modeling. Familiarity with RTL BFM modeling, UVM, SC/TLM, EDA tool development, logic design verification, and AI coding tools is preferred.

Develop digital infrastructure and early-stage physical design flows for 3D-IC applications, focusing on pre-place-and-route methodology. Collaborate with customers and foundry partners to translate advanced-node requirements into software solutions. Build and debug large-scale software using Java, Tcl, shell scripting, and some C++. Optimize performance, capacity, and usability while working with legacy codebases, large datasets, and cross-functional teams.

Develop digital central solutions and early-stage physical design flows for 3D-IC applications, with emphasis on pre-place-and-route methodology. Collaborate with customers and foundry partners to translate advanced design requirements into software solutions. Build and optimize large-scale infrastructure, debug legacy code, and apply software engineering fundamentals across Java, Tcl, shell scripting, and C++.

Develop and maintain high-quality C/C++ software for hardware-software co-simulation, including compiler and runtime components for Transaction-Based Acceleration. Support existing features and create capabilities for Palladium and Protium emulation systems. Collaborate with field application engineers to deploy high-performance solutions on Cadence emulation and prototyping platforms while debugging complex system-level issues with global teams.