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Manage multiple large semiconductor accounts as an inside sales representative: coordinate sales logistics, run reports and forecasts, maintain CRM account profiles, handle order management (samples, orders, backlog, reschedules, shipments, RMAs), analyze backlog/demand/supply/inventory, and liaise with clients, field teams, factories, distributors to drive design wins to revenue and ensure customer satisfaction.

Lead Process, Equipment, and Yield Engineering teams in a wafer fab to drive yield improvement, equipment reliability, production alignment, and continuous process optimization. Provide technical leadership, cross-functional collaboration, and coaching while implementing SPC, root-cause analysis, and preventive maintenance to meet operational and delivery targets.

Develop and validate ATE test programs and high-speed low-noise test boards for timing products (SyncE/1588, clock distribution, frequency synthesizers). Support product characterization, manufacturing ramps, yield and cost improvements, customer returns analysis, subcontractor test activity, and cross-functional releases from specification through volume manufacturing.

Lead development and scaling of RTL-to-silicon implementation methodologies for 12nm hierarchical SoCs and multi-die designs. Own synthesis, UPF-based low-power flows, timing convergence, constraint development, floorplanning collaboration, and mentor teams to ensure predictable signoff and first-generation product readiness.

Lead design, develop, test, deploy, and support custom enterprise applications, reporting, and ETL for manufacturing and engineering. Serve as technical lead, mentor team members, create documentation, manage projects, support multiple global sites, and supervise staff at the Colorado Springs FAB5 facility.

Lead design, development, testing, deployment, and support of .NET-based enterprise applications, reporting and ETL for manufacturing and engineering; act as technical lead, mentor teammates, manage projects, create documentation, and support multiple global sites. On-site in Gresham, OR; occasional off-hours meetings required.

Lead verification of complex SoC and FPGA subsystems using constrained-random, formal and C-based methods. Develop reusable UVM testbenches, integrate AI/ML verification tools, collaborate with emulation/prototyping and architecture teams, and mentor junior engineers to ensure first-silicon success.

Design and maintain reusable UVM-based testbenches and verification environments for next-generation secure, low-power FPGAs. Perform constrained-random, formal and C-based verification, RTL and power-aware verification, collaborate with emulation, prototyping, architecture and design teams, and apply AI/ML-enabled verification techniques to improve coverage and productivity.

Lead digital design, DFT, physical implementation, and static timing analysis for macros and full-chip SoCs. Drive RTL-to-netlist flows, develop synthesis/STA/layout constraints, coordinate with RTL/DFT/APR teams, ensure signoff across multiple modes and corners, and deliver tapeout-quality results on advanced process nodes.

The role involves defining Mixed-Signal IP requirements, managing integration processes, supporting debug for analog circuits, and designing CMOS integrated circuits.