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Define and lead verification strategy and plans, develop SystemVerilog/UVM environments for blocks and SoCs, coordinate verification activities, debug RTL functional issues, and improve verification methodology.

Lead verification strategy and plans for mixed-signal IP and SoC blocks. Develop SystemVerilog/UVM environments, coordinate verification activities, debug RTL functional issues, collect coverage, manage regressions, and improve verification methodology.

Lead verification strategy and plans for blocks and SoCs; develop SystemVerilog/UVM environments; coordinate and lead verification activities; debug RTL functional issues; improve verification methodology and manage coverage and regressions.

Lead and define verification strategies and plans for digital/SoC blocks, develop SystemVerilog/UVM environments, debug RTL functional issues, coordinate verification activities, and improve verification methodology.

Lead Americas mass-market regional marketing and business development to drive customer engagement, design-ins/wins, and revenue growth. Build executive and engineering relationships with customers, distributors, and cross-functional teams; run regional programs, events, and funnel management; influence product roadmaps through market intelligence; and travel extensively to support strategic initiatives across the Americas.

Lead and manage an analog/mixed-signal design team to develop power-management and clock-management CMOS IP. Drive circuit design, layout, verification, DFT strategy, lab debug, validation support, documentation, cross-functional coordination, and mentor junior engineers to deliver production-quality IP on schedule.

Lead development, verification, layout, and characterization of advanced analog and mixed-signal CMOS IP (bandgaps, amplifiers, LDOs, PLLs, etc.). Drive specifications, debug in lab, perform bench characterization, collaborate with cross-functional teams, mentor junior engineers, and ensure designs meet performance, power, reliability, and production release goals.

Perform reliability evaluation and failure analysis of drivetrain power modules for automotive EVs. Apply AQG324 power-cycle stress strategies, configure and debug power-cycle and fluid delivery test systems, run reliability tests (PCT, HTRB, HTGB, SCIS, UIS), generate stress reports, and collaborate with cross-functional teams to support qualification and lifetime assessment.

The Technical Marketing Engineer oversees new product ownership, analyzes market needs, defines products, initiates projects, and maintains business growth in intelligent power modules for automotive and industrial applications.

Lead the EM Test Operation team to enhance test competencies for External Manufacturing, driving continuous improvements and supporting strategic projects in semiconductor testing.