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Develop and optimize scalable LLM inference software across GPU platforms. Perform performance analysis, tuning, and testing. Collaborate with research, software, and product teams to guide inference architecture and hardware design; follow academic advances and publish results.

Lead research and engineering for Nemotron post-training pipelines: develop synthetic data and agentic RL algorithms, build large-scale data and training infrastructure, collaborate on vendor data acquisition, optimize inference/deployment, and publish results.

Lead technical vision and strategy for next-generation graphics developer tools. Design and prototype tooling, drive cross-team initiatives, mentor engineers, engage external developers and partners, and deliver production-ready solutions that improve graphics development, debugging, profiling, and optimization workflows.

Lead SoC design and integration for networking DPUs and switch silicon. Define project milestones, develop system-level methodologies and IP, coordinate cross-functional teams, integrate subsystem pieces, and deliver models for verification across cluster/subsystem/SoC/emulation stages.

Design and implement verification environments for next-generation NVIDIA networking/GPU chips. Collaborate with cross-functional teams on ASIC verification, build testbenches, validate protocols and ensure chip controller functionality and reliability.

Lead end-to-end supply planning strategy and governance for networking products (optics, switches, adapters). Build scalable planning frameworks across chips, memory, capacity, and manufacturing; ensure data integrity (BOMs, yields, cycle times); accelerate time-to-market via complexity reduction and AI-enabled planning; and manage and develop global supply planning teams.

Lead a team that evaluates, integrates, and supports third-party EDA tools and workflows for mixed-signal circuit design. Drive vendor relationships and roadmap alignment, promote adoption through training and integration, and apply agentic-AI where it improves efficiency. Provide people leadership, technical direction, and cross-team collaboration to improve design quality and reduce cycle time.

Lead wafer- and package-level NPI bring-up for SoCs, drive ATE test strategy and bring-up, define silicon characterization plans (scan, MBIST, IO BIST, functional), analyze yield limiters and ATE failures, characterize performance and power, and lead cross-functional root-cause and improvement efforts with design, foundry, quality, test, customers and suppliers.

Lead the NIC firmware verification infrastructure team to ensure stable, scalable testing and high-quality deliverables. Own verification domain, drive testing methodologies and CI, mentor engineers, set priorities, remove blockers, participate in design and code reviews, and collaborate with NIC FW teams to evaluate feature data and control paths.

Lead development of full-chip physical design methodologies and physical verification flows for networking SoCs. Drive tapeout activities, debug and approve PV runs (DRC/LVS/ANT/ERC/DFM), collaborate with layout/block owners and project managers, and develop/maintain EDA flow and tool methodologies across projects.