Top Tech Jobs & Startup Jobs

Design and verify memory layouts for advanced CMOS processes, including floor planning, hierarchical layout, chip integration, and physical verification. Manage schedules and end-to-end deliverables while applying process rules and layout guidelines. Collaborate with SOC and library teams, support new methodology reviews, and lead or train junior engineers. Experience with memory architecture, memory compilers, signal and power planning, and automation is valuable.

Leads cross-functional engineering projects developing RF antenna tuner products for Tier-1 mobile customers. Responsibilities include managing project timelines, resources, risks, and milestones; serving as the primary technical customer contact; and guiding module debugging, impedance and aperture tuning, and RF optimization through mass production.

Designs complex flip-chip BGA packages for high-performance ASICs used in AI, networking, HPC, and 5G applications. Responsibilities include package layout, signal and power integrity, thermal and reliability considerations, manufacturability, and design of SerDes, ADC/DAC, DDR, and related structures. The engineer manages multiple projects, collaborates with global teams and vendors, interfaces with customers, and improves design processes through automation and documentation. This is a fully onsite role.

Leads digital IC design or mixed-signal verification for semiconductor ASICs. Responsibilities include defining digital architectures, RTL coding, synthesis, formal verification, timing analysis, place and route, UVM-based testbench development, coverage closure, analog-digital modeling, and verification automation. The role coordinates global engineering teams, supports product qualification and manufacturing release, conducts design reviews, and drives AI-assisted methodology improvements.

Leads enterprise Kubernetes and AI infrastructure modernization engagements from architecture through production rollout. Deploys and troubleshoots VKS clusters, GPU-accelerated AI workloads, stateful data platforms, messaging systems, and legacy migrations. Writes production code and prototypes in customer environments, collaborates with core engineering and product teams, and translates field issues into platform improvements. Requires extensive experience with Kubernetes distributions, cloud-native data and AI tooling, distributed systems, infrastructure as code, and GitOps.

Embeds with enterprise engineering teams to architect, deploy, migrate, and troubleshoot production Kubernetes platforms and AI infrastructure. Responsibilities include modernizing bare-metal and legacy workloads, operating GPU-enabled clusters, deploying data and AI services, migrating stateful systems, and supporting multi-cloud Kubernetes environments. The role writes production code, develops integrations, resolves field issues, and translates customer feedback into product requirements for core engineering teams. It requires deep distributed systems, cloud-native, infrastructure-as-code, GitOps, and enterprise engagement expertise.

Leads enterprise infrastructure modernization, Kubernetes and VMware architecture, distributed AI inferencing, large-scale migrations, and stateful workload deployments. Acts as a technical bridge between engineering, product leadership, and executive customers; develops production code, operators, and reference implementations; influences product roadmaps; establishes GitOps and deployment standards; and mentors senior engineers. Requires deep expertise in Kubernetes, cloud-native platforms, GPU infrastructure, distributed systems, multi-cloud interoperability, and legacy-to-cloud migration.

Lead enterprise infrastructure modernization and AI platform deployments as a principal field engineering authority. Architect Kubernetes, VMware, GPU, distributed systems, and multi-cloud environments; guide large-scale migrations from legacy bare metal and stateful platforms; develop production operators and integrations; influence product roadmaps through customer feedback; establish deployment standards; and mentor senior field engineers.

Lead and participate in complex ASIC physical implementations across synthesis, DFT, floorplanning, P&R, clock and power methodology, timing closure, signal integrity, and physical verification using multiple EDA tool flows.

Design Engineer on Broadcom's Custom Silicon Design Team working on physical implementation of high-performance ASICs (3 nm and below). Responsibilities include floorplanning, placement, clock tree synthesis, routing, timing closure, physical verification, and signoff. Work in UNIX environments, use TCL (Python/Perl preferred) and commercial/in-house EDA tools, collaborate cross-functionally, and contribute to design flow automation and silicon bring-up. Requires Electrical/Electronics Engineering degree and strong VLSI/ASIC fundamentals.