Top Tech Jobs & Startup Jobs

Own full-chip static timing sign-off and closure for advanced ASICs across PVT corners, functional and test modes. Develop SDC constraints, manage MMMC and OCV analysis, triage timing violations, drive ECOs, and collaborate with RTL, physical design, and DFT teams to optimize PPA. Apply Tcl, Python, Perl, Shell, AI/ML automation, and data-mining workflows to reduce runtime, improve infrastructure efficiency, and support timing closure at leading-edge process nodes.

Performs ASIC and SoC physical design implementation, including floor planning, partitioning, placement, clock tree synthesis, routing, timing analysis and closure, physical verification, equivalence checks, power optimization, and ECO implementation. Drives design tools and methodologies to meet PPA targets and Broadcom tapeout quality standards. Requires extensive block- and SoC-level implementation experience and collaboration in global engineering teams.

Lead STA and synthesis engineering for complex SoC, ASIC, IP, digital, and mixed-signal blocks in advanced technology nodes. Responsibilities include developing and validating timing constraints, performing static timing analysis and audits, executing synthesis, defining signoff methodologies, analyzing QoR, automating workflows with Tcl or Perl, optimizing clock trees, generating timing ECOs, and driving final timing closure.

Supports physical implementation of advanced ASICs, including floorplanning, placement and routing, clock-tree synthesis, static timing analysis, timing closure, physical verification, IR drop and electromigration analysis, and signoff. Develops automation scripts in TCL, Python, Ruby, or Bash. The role focuses on next-generation networking, AI/ML, and cloud ASICs using advanced semiconductor nodes and EDA tools.

Executes ASIC physical design tasks including block-level floorplanning, placement and routing, clock tree synthesis, static timing analysis, timing closure, physical verification, IR drop and electromigration analysis, and signoff. Develops TCL, Python, Ruby, or Bash automation scripts to improve EDA workflows. The role supports advanced networking, AI/ML, and cloud ASICs using leading-edge semiconductor nodes.

Leads full-chip and block-level ASIC physical design from floorplanning through GDSII tapeout. Responsibilities include synthesis, placement, routing, clock tree synthesis, timing and power closure, signal integrity, IR-drop and electromigration signoff across advanced nodes. The role uses Cadence, Synopsys, Siemens, and extraction tools while developing automation with TCL, Python, and Unix shell scripting. Requires technical leadership and extensive experience taping out complex networking or AI ASICs.

Develop, test, deploy, and support software tools and methodologies for ASIC design automation. Automate synthesis, place-and-route, verification, and other IC development processes using scripting and C/C++. Debug tool and design-flow issues, support engineers globally, collaborate with EDA vendors, and create documentation and training. The role requires digital logic and Verilog knowledge, software development skills, and understanding of timing and power analysis.

Develop and validate VMware ESX platform features, including vmkernel and userspace components, with emphasis on scalability, performance, reliability, hardware support, and automation. Design advanced test strategies, implement coverage for virtualization products, debug low-level operating system issues, and collaborate with engineering teams. The role offers increasing ownership of validation projects and requires strong systems software, kernel, virtualization, hardware architecture, Python, and C expertise.

Leads global engineering teams developing Private AI products and services, integrating with vSphere, NSX, and vSAN. Owns platform reliability, security, lifecycle management, SDLC execution, and day-two operations. Defines Broadcom’s upstream contribution strategy and represents the company in the Kubernetes and CNCF ecosystems. Requires deep Kubernetes expertise, significant open-source influence, distributed-systems experience, and global engineering leadership.

Contribute to physical implementation of large-scale CMOS ASICs, including floorplanning, placement, clock tree synthesis, routing, timing closure, physical verification, power planning, and design signoff. Collaborate with cross-functional teams, use commercial and internal EDA tools, improve design automation and methodologies, and support the ASIC lifecycle from RTL through GDSII and silicon bring-up.