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Regional account manager responsible for identifying and winning custom ASIC and silicon opportunities across APJ. Drive account strategy, executive relationships, long-cycle deal execution, pipeline and forecasting, competitive intelligence, and influence product roadmaps while partnering with internal teams to deliver scalable, profitable custom silicon solutions.

Develop and optimize capillary underfill (CUF) module assembly processes and equipment to meet quality, reliability, yield, cost, and manufacturability targets. Design experiments, analyze data, create specifications, validate materials/equipment, run reliability/environmental tests, and collaborate with suppliers and cross-functional teams to standardize qualification and improve packaging processes.

Develop and prototype on-device AI solutions (LLMs, VLMs, AI Agents), build inference pipelines and media codecs, perform hardware-software co-optimization for CPU/GPU/NPU, and collaborate across model and hardware teams to move prototypes to product.

Develop and prototype on-device AI solutions (LLMs/VLMs/Agents), build inference pipelines, media codecs and automation tooling in Python/C/C++. Integrate and optimize models for CPU/GPU/NPU, perform system-level hardware-software co-optimization, and collaborate with global model and hardware teams to scale production-ready deployments.

Design and debug CPU circuits at the transistor level, optimize designs, and collaborate with teams to meet power and performance targets.

Drive custom ASIC and silicon sales across the Americas: define regional GTM strategy, build executive relationships, manage long-cycle technical deals, shape solutions with internal partners, develop pipeline and forecasts, influence roadmaps, and close high-value custom silicon opportunities.

Lead architecture and design of power-management firmware for Intel SoCs. Define firmware frameworks and specs, develop algorithms and HW/SW interfaces, guide vulnerability assessments, mentor firmware teams, evaluate new technologies, and drive research aligned to product power-efficiency and performance goals.

Perform hands-on lab failure analysis and electrical fault isolation for packaged semiconductor assemblies, develop and apply characterization techniques, recommend corrective actions, collaborate across teams to improve yield, and support program milestones on a required on-site shift schedule.

Perform hands-on failure analysis and root-cause determination for assembled package yield loss and in-line failures. Conduct electrical fault isolation, defect characterization, data acquisition and analysis, and recommend corrective actions. Develop failure analysis techniques and best practices, collaborate across teams and customers, and support program milestones. Lab-based role requiring on-site shift work and clear communication of findings to yield and integration stakeholders.

This role offers fresh graduates opportunities to engage in diverse engineering projects, enhancing skills in digital design, software development, and data analysis while collaborating with cross-functional teams.