Top Tech Jobs & Startup Jobs

Design, develop, and optimize cloud and AI server/rack platforms by integrating software, firmware, board, and silicon components. Debug system-level issues, improve fleet quality and performance, develop automation and AI-driven engineering solutions, and collaborate cross-functionally to meet customer requirements and implement scalable, reliable systems.

Drive yield improvement across technology nodes by analyzing large datasets, identifying defect modes and root causes, developing multivariate and ML algorithms, performing fault isolation and failure analysis, collaborating with cross-functional teams, and implementing process changes and tools to meet yield milestones and support new product introductions.

Drive APJ Edge ISV adoption by identifying and onboarding ISV partners, mapping solutions to Intel Edge software, advising on architecture (OEP/Edge AI Suites), coordinating events and early-access enablement, and aligning commercial packaging and channel scale across the region.

Lead design and implement a scalable chassis automation tool that translates SoC architecture requirements into generated RTL, registers, verification collateral, and integration artifacts. Collaborate with architecture, RTL, verification, and integration teams, enable PPA analysis, integrate with front-end/back-end flows, and mentor junior engineers to deliver high-quality automated outputs.

Define end-to-end CPU architecture and microarchitecture features, set performance/power/area targets, model and analyze CPU performance and power, develop tests and simulations, specify new instructions, and collaborate with design, verification, and validation teams to deliver optimized CPU designs across product segments.

Lead supplier development and qualification for advanced substrate and wafer assembly technologies. Drive technical enablement across process steps (embedding, drilling, plating, lithography, metrology, electrical testing), manage readiness milestones, implement factory validation and yield-improvement plans, create micro schedules for new factory startups, and monitor ramp indicators to ensure incident-free production ramp and capacity introduction.

Lead development, validation, and sign-off of SPICE/compact models for advanced process nodes. Define extraction methodologies, automate QA and validation flows, architect test structures for model-to-hardware correlation, own documentation and training, and mentor junior engineers while aligning cross-functional stakeholders and EDA partners on modeling strategy.

Drive adoption of Intel Edge-to-Cloud and server/data-center solutions with Japanese enterprise customers and partners. Build technical relationships, develop tailored solutions, lead infrastructure architecture discussions, influence executive stakeholders, identify market opportunities, and present at industry forums to grow Intel's market share and inform product strategy.

Lead end-to-end verification for chassis and interconnect IPs, build scalable UVM/SystemVerilog testbenches, drive simulation/formal convergence and coverage closure, collaborate with architecture/design/software, mentor engineers, and ensure functional signoff and performance/power goals.

Lead supplier qualification, capacity ramp and yield improvement for advanced substrate packaging (EMIB-T). Manage supplier partnerships, reduce lead times and TPT, oversee TV/product deliveries and factory startups, enforce PCS commitments, and influence senior supplier decisions to ensure on-time, incident-free production ramps.