Spice Modeling Engineer

Posted One Month Ago
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Bangalore, Bengaluru Urban, Karnataka, IND
In-Office
Senior level
Artificial Intelligence • Cloud • Information Technology • Software
Creating world-changing technology that enriches the lives of every person on earth.
The Role
Lead development, validation, and sign-off of SPICE/compact models for advanced process nodes. Define extraction methodologies, automate QA and validation flows, architect test structures for model-to-hardware correlation, own documentation and training, and mentor junior engineers while aligning cross-functional stakeholders and EDA partners on modeling strategy.
Summary Generated by Built In
Job Details:

Job Description: The Role and Impact As a Senior Spice Modeling Engineer, you will own the development, validation, and strategic direction of SPICE models that enable Intel's advanced process technologies. You will define modeling methodologies, resolve complex customer and cross-team technical issues, and drive improvements to modeling infrastructure and tools across the organization. Business Group You will join Intel's Design Technology Platform (DTP) - Process Design Kit (PDK) team. This team develops and delivers the technology, tools, and methodologies required for efficient, high-quality design across Intel products. Working closely with Technology Development, Product Design teams, and EDA partners, the group drives design enablement for Intel's latest process technologies. Key Responsibilities - Own and drive development of SPICE model files for advanced process nodes, partnering directly with Extraction, Technology Development, and Library leads to resolve complex technical trade-offs - Define and drive automation strategy for QA flows to improve validation coverage, efficiency, and scalability across the team - Architect and optimize test structures for model-to-hardware correlation and parasitic extraction, setting standards for the broader team - Author and own documentation, guidelines, and training materials that establish best practices across the org - Define methodologies to extract SPICE model parameters from IV and CV data, and represent the team in technical sign-off discussions with internal and external stakeholders - Partner with technology development and design engineering leadership to shape circuit tools, compact model strategy, and process file direction - Provide technical mentorship to junior engineers and contribute to team technical roadmap

Qualifications:

Minimum Qualifications
Master's degree with 6+ years of experience, or PhD with 3+ years of experience, in Electrical Engineering, Microelectronics, or a related field with a focus on semiconductor device physics, including substantial hands-on experience developing, validating, and driving sign-off of compact/SPICE models within a foundry PDK environment.
Preferred Qualifications
1. Demonstrated track record of leading compact modeling methodology decisions (e.g., model sign-off criteria, extraction methodology) at advanced/leading-edge process nodes
2. Strong Python scripting skills, with experience building or owning modeling automation infrastructure
3. Experience representing technical work to customers, cross-functional leadership, or external partners
4. Excellent written and verbal communication skills, with demonstrated ability to align cross-org stakeholders on technical direction

          

Job Type:Experienced Hire

Shift:Shift 1 (India)

Primary Location: India, Bangalore

Additional Locations:

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Skills Required

  • Master's degree with 6+ years or PhD with 3+ years in Electrical Engineering, Microelectronics, or related field
  • Focus on semiconductor device physics
  • Hands-on experience developing, validating, and driving sign-off of compact/SPICE models within a foundry PDK environment
  • Demonstrated leadership in compact modeling methodology decisions at advanced process nodes
  • Strong Python scripting skills and experience building or owning modeling automation infrastructure
  • Experience presenting technical work to customers, cross-functional leadership, or external partners
  • Excellent written and verbal communication and ability to align cross-organizational stakeholders

Intel Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Intel and has not been reviewed or approved by Intel.

  • Leave & Time Off Breadth — Sabbaticals and paid time off are highlighted as signature elements, with an established program offering four weeks after four years or eight weeks after seven years. This distinctive time off is positioned as a meaningful part of the overall package.
  • Parental & Family Support — Paid bonding leave of 12 weeks and a New Parent Reintegration program, plus fertility benefits around $40,000 and up to $15,000 adoption reimbursement with no lifetime cap, are clearly stated. These programs are presented as standout components alongside broader family support resources.
  • Healthcare Strength — Multiple medical plan options with 2026 updates, a shift to Spring Health for EAP, and in‑network virtual medical visits covered at 100% beginning in 2026 indicate a comprehensive offering. These features signal an emphasis on robust medical access and mental health support.

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The Company
HQ: Santa Clara, CA
75,000 Employees
Year Founded: 1968

What We Do

Our mission is to shape the future of technology to help create a better future for the entire world, that’s the power of Intel Inside. With more ingenuity and creativity inside, our work is at the heart of countless innovations. From major breakthroughs to things that make everyday life better— they’re all powered by Intel technology. With a career at Intel, you can help make the future more wonderful for everyone.

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