Top Tech Jobs & Startup Jobs

Leads design verification for radar IP, subsystems, and SoCs from specification through post-silicon validation. Owns verification strategy, methodology, environments, coverage, regressions, traceability, and signoff across multiple programs. Builds and mentors verification teams, collaborates with architecture, RTL, physical design, firmware, systems, and applications teams, and supports customer reviews and ISO 26262/ISO 21434 certifications. The role requires expertise in SystemVerilog/UVM, C-based verification, digital design, protocols, formal verification, and post-silicon debugging.

Drives forecasting, budgeting, variance analysis, monthly financial reporting, cost analysis, capital expenditure evaluation, and financial modeling for a manufacturing facility. Partners with factory leadership, the controller, operations, planning, and procurement to improve cost efficiency and financial performance. Supports audits, reporting compliance, process improvements, dashboards, and ad hoc financial analysis.

Leads a test engineering team responsible for developing and optimizing production tests for precision ADCs. Drives test strategies, cost reduction, yield improvement, DFT, validation, failure analysis, qualification, and tester-agnostic methods. Analyzes test data, resolves technical issues, collaborates across design, manufacturing, quality, and reliability teams, and coaches product and test engineers.

Develops probe and final test solutions for complex mixed-signal DAC, ADC, and other integrated devices. Responsibilities include creating test plans and programs, designing ATE interface hardware, debugging and characterizing silicon, analyzing yield and failures, optimizing test time, supporting qualification and validation, and releasing products to volume production. The role collaborates with design and manufacturing teams to deliver robust, cost-effective test solutions.

Evaluates, selects, installs, upgrades, maintains, and supports semiconductor CVD/PVD manufacturing equipment. Improves equipment uptime and reliability, investigates manufacturing-impacting issues, monitors technical and safety updates, supports repair and process engineering teams, and develops preventive maintenance schedules. Requires semiconductor cleanroom experience, vacuum equipment knowledge, SPC familiarity, analytical problem-solving, collaboration, and strong project execution skills.

Perform hands-on analog and power IC layout for high-density PMICs, including matching, symmetry, current density, electromigration, IR drop, high-voltage isolation, parasitic-aware design, power devices, bond pads, and ESD structures. Collaborate with circuit designers, complete DRC/LVS/PEX verification, adopt new tools and flows, improve design processes, and deliver high-quality layouts on schedule.

Develop verification plans and mixed-signal testbenches for analog and mixed-signal ICs using Cadence Virtuoso and SystemVerilog. Create automated checks, measurements, coverage regressions, and specification compliance matrices; report results, track issues, and drive bugs to closure with cross-functional design teams. The role includes regression scripting, verification-flow improvements, and structured training through TI’s Career Accelerator Program.

Leads design verification for high-speed SerDes transceivers used in automotive, industrial, enterprise, and consumer electronics. Applies digital design and modeling knowledge, debugs complex signal-conditioning and data-path designs, and supports reliable, low-power semiconductor development in advanced CMOS processes.

Evaluates, selects, installs, upgrades, maintains, and supports semiconductor manufacturing equipment. The role monitors equipment performance and reliability, improves uptime, resolves manufacturing-impacting equipment issues, supports repair and process engineering teams, and develops preventive maintenance programs. Expertise with semiconductor equipment, vacuum technologies, cleanroom protocols, SPC, and equipment monitoring is preferred.

Develops and implements probe and final tests for complex mixed-signal power management devices. Responsibilities include creating test plans and programs, designing ATE interface hardware, characterizing and debugging silicon, analyzing yield and failure data, optimizing test time, supporting qualification, and transitioning products to volume production. The role requires electrical engineering expertise, analog ATE experience, circuit knowledge, laboratory equipment skills, and product engineering experience.