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Serve as Micron's senior GRC and cyber resilience leader for Japan, driving adoption of governance, cybersecurity, risk management, compliance, audit, and regulatory programs. Liaise between global GRC and regional stakeholders, lead audits and risk assessments, manage remediation, develop executive reporting and dashboards, and champion AI-enabled automation for assessments and evidence management. Represent the region to customers, regulators, and auditors while ensuring alignment with corporate strategy and local regulatory/cultural requirements.

Leads global semiconductor wet-process productivity, yield, quality, cost, and sustainability improvements. Drives process and hardware optimization, chemistry and technology qualification, defect and particle reduction, equipment performance benchmarking, tool start-up acceptance criteria, CIP roadmaps, IoT-based excursion prevention, and energy, water, and waste reduction initiatives. Collaborates with suppliers, facilities, and cross-functional teams to mature equipment, establish process parameters, and implement scalable solutions across Micron sites.

Leads the design, integration, and silicon delivery of analog and mixed-signal IP for HBM logic dies. Responsibilities include designing high-speed interfaces, clocking, SerDes, biasing, calibration, and power circuits; defining interfaces and power domains; conducting simulation and reliability analyses; guiding layout, floorplanning, matching, shielding, and EM/IR compliance; signing off layouts; optimizing designs for advanced nodes; and collaborating with digital, systems, packaging, and test teams.

Performs electrical and semiconductor failure analysis to identify yield detractors, determine root causes, and recommend corrective actions. Develops yield monitoring methods, automated analytics, dashboards, anomaly detection models, and AI-enabled workflows. Partners with cross-functional engineering and manufacturing teams on yield improvement, product qualification, technology transfers, and technical reviews. Operates laboratory equipment, documents findings, supports process improvements, and trains engineers and technicians.

The EUV Lithography Pathfinding Engineer will evaluate advanced lithography technologies, lead pathfinding activities, collaborate on roadmap requirements, and ensure implementation readiness for new patterning approaches.

Develops, integrates, tests, debugs, and validates firmware for high-performance SSD controllers. The role performs failure analysis, root-cause investigation, defect isolation, and optimization for performance, reliability, latency, power efficiency, and product quality. Responsibilities include collaborating with hardware and systems teams, maintaining firmware tests, documenting technical findings, supporting product development, mentoring junior engineers, and applying AI-assisted tools responsibly.

Designs and owns high-performance analog and mixed-signal circuits for High Bandwidth Memory PHYs, including transmitters, receivers, clocking, SerDes, references, calibration, and power regulation. Performs pre- and post-layout simulation, variation and reliability analysis, layout review, and advanced-node optimization. Collaborates with layout, digital, systems, packaging, and test teams while supporting silicon bring-up and production delivery.

Launch, design, develop, characterize, install, upgrade, and improve CMP/BOND semiconductor manufacturing equipment. Lead equipment setup, process capability improvements, cost reduction, parameter establishment, abnormality analysis, vendor collaboration, project management, technical documentation, and audit support while maintaining safety and quality standards.

Supports semiconductor fab equipment installation, upgrades, maintenance, troubleshooting, and reliability improvement for RDA and metrology tools. Leads root-cause investigations, preventive maintenance scheduling, equipment performance analysis, project prioritization, capacity planning, vendor coordination, and continuous improvement initiatives. Uses analytics, automation, visualization, and AI to improve uptime, predictive maintenance, reporting, throughput, and equipment health.

Develops and refines chemical mechanical planarization processes to improve semiconductor performance and yield. Analyzes process data to identify variation root causes, implements corrective actions, collaborates cross-functionally on improvements, and ensures compliance with industry standards and safety regulations. Uses AI-assisted tools responsibly to improve efficiency, quality, research, analysis, and problem-solving.