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Verify Velaura’s next-generation Physical AI SoC from RTL blocks through complete HW/SW systems. Responsibilities include developing SystemVerilog and UVM environments, assertions, coverage, formal verification, emulation, FPGA prototyping, performance and safety validation, post-silicon debug, and root-cause analysis. The role covers compute engines, memory, interconnects, processors, DMA, firmware, drivers, and operating-system interactions while collaborating across architecture, RTL, software, and systems teams.

Lead architecture and development of an AI accelerator compiler stack, including model ingestion, graph lowering, optimization, quantization, code generation, partitioning, diagnostics, and verification. Partner with hardware, firmware, runtime, and model teams to optimize executable artifacts for NPUs. Lead hiring, mentoring, and technical direction for compiler and ML systems engineers.

Leads DFT architecture, methodology, implementation, verification, sign-off, silicon bring-up, and production ramp for complex AI and high-performance ASIC/SoC designs. Oversees scan, ATPG, MBIST, LBIST, JTAG, fault simulation, coverage closure, memory repair, timing, and test-mode integration. Partners across RTL, verification, physical design, STA, validation, manufacturing, and product engineering. Drives DFT tools and automation, post-silicon diagnosis, yield improvement, quality metrics, and team leadership.

Own functional verification of custom CPU units from test planning through coverage closure. Build SystemVerilog and UVM environments with C/C++, stimulus, checkers, assertions, and coverage. Verify instruction execution, caches, memory ordering, coherence, exceptions, privilege behavior, performance, and reliability. Run regressions, support emulation and FPGA prototyping, enable pre-silicon software bring-up, and perform hardware-software root cause analysis.