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Manages the complete participant journey for an executive education program, serving as the primary contact for senior professionals. Responsibilities include onboarding, advisory support, relationship management, issue resolution, stakeholder coordination, documentation, engagement tracking, reporting, and operational follow-up. The role requires polished communication, executive presence, and experience in education, EdTech, program operations, learner success, admissions, counseling, or customer relationship management.

Manages customer accounts receivable, monitors ageing and overdue invoices, conducts payment follow-ups, reconciles accounts, resolves billing discrepancies, tracks invoices and payment commitments, maintains collection records, prepares AR reports, handles customer queries, escalates disputed balances, and supports month-end closing activities.

Reviews customer applications for credit and risk screening, verifies KYC and financial documents, validates business information, examines bank statements, ITRs and credit reports, maintains case records and MIS, coordinates document collection, prepares cases for further assessment, and escalates exceptions or risk indicators.

Own synthesis and static timing analysis from RTL through tapeout, including constraint development, equivalence checks, timing signoff, ECOs, and timing closure across design levels. Partner with RTL and Physical Design teams on SoC closure and lead a team of 4–5 engineers. The role requires strong TCL scripting, Unix skills, and expertise in timing signoff flows and constraints.

Own DFT architecture and implementation from RTL through tapeout, including scan insertion, ATPG, fault coverage, MBIST/LBIST, boundary scan, scan compression, and test-point insertion. Debug silicon test failures, correlate results with simulations, drive testability closure with design and physical teams, and mentor 3–4 engineers.

Physical Design Engineer responsible for VLSI backend implementation from RTL handoff through tapeout. Duties include floorplanning, power planning, placement, clock tree synthesis, routing, timing closure, physical verification, DRC/LVS cleanup, ECO implementation, and signoff checks. The role collaborates with STA, DFT, and RTL teams on block-level closure and supports full-chip integration activities.

Own synthesis and static timing analysis across design blocks from RTL through tapeout. Responsibilities include logic-aware synthesis, equivalence checks, VCLP signoff, constraint development, timing closure across corners and modes, manual ECOs, and resolving timing and DRC violations. The role also leads a team of 4–5 engineers and collaborates with RTL and physical design teams on SoC timing closure.

Perform VLSI physical design from RTL handoff through tapeout, including floorplanning, power planning, placement, clock tree synthesis, routing, timing closure, physical verification, ECO implementation, and DRC/LVS signoff. Collaborate with STA, DFT, and RTL teams on block-level closure and support full-chip integration activities.

Own synthesis and static timing analysis across design blocks, driving timing signoff from RTL through tapeout. Develop SDC and UPF constraints, perform equivalence checks, close timing across corners and modes, generate manual ECOs, and resolve timing and DRC violations. Lead a team of 4–5 engineers and collaborate with RTL and Physical Design teams on block, subsystem, and full-chip SoC timing closure.

Own DFT architecture and implementation from RTL through tapeout, including scan insertion, ATPG, MBIST/LBIST, boundary scan, compression, test-point insertion, fault coverage, and silicon debug. Collaborate with RTL, physical design, and STA teams to achieve testability closure, while leading and mentoring 3–4 DFT engineers.