Lead microarchitecture and subsystem design for edge compute chips, owning PPA, timing, area, and power tradeoffs; establish verification and signoff practices; encode design judgment into tooling; use AI and frontier models to accelerate development; collaborate with founders and researchers to drive chips to tapeout.

Build and maintain the internal platform and tooling used by hardware engineers, including robust data pipelines, backend services, and containerized workflows. Work across the stack to turn hardware workflows into reliable, production-ready software while leveraging AI to accelerate development.

Design and own the hardware/software interface for edge compute chips, develop firmware/drivers and runtimes for bring-up, make HW/SW tradeoffs, and validate subsystems across emulation, FPGA, and hardware bring-up.