Phinity is an AI research lab focused on solving chip design. The bottleneck to AGI is compute, and we enable AI agents to tape-out chips autonomously, from architecture to post-silicon. We are building RL environments, agent infrastructure, and evaluation systems to accomplish this. Our team brings together deep AI and silicon expertise, including leaders and executives from top chip companies, post-training chip-design models at NVIDIA, AI for formal verification research, previous exits, and over 10 years of experience building chips at NVIDIA, Intel, Mediatek, and others.
We are hiring a Research Engineer to develop data in order to train and evaluate agents on hardware tasks.
You will
Build and scale out generation of novel, experimental environments for testing agents in real-world hardware engineering tasks
Profile and benchmark unreleased models
Run and experiment on research problems at the intersection of hardware engineering and reinforcement learning
What we’re looking for
Prior low-level systems and/or VLSI experience
Good research intuitions and rigorous engineering skills
Leadership skills; high ownership
ML/RL background is a plus
Operational experience is a plus
Why Phinity
Work directly with frontier AI labs to re-imagine ASIC design–see the frontier of intelligence before anyone else
Collaborate with our AI researchers and HW experts, with high leverage and ownership to develop new technologies
Benefits include
Health insurance
Retirement plans
Unlimited PTO
Paid parental leave
Lunch and dinner provided in-office
Skills Required
- Prior low-level systems and/or VLSI experience
- Good research intuitions and rigorous engineering skills
- Leadership skills and high ownership
- Machine learning or reinforcement learning background
- Operational experience
What We Do
Phinity Labs is building foundational training infrastructure for autonomous chip design. Its AI agents are intended to design, verify, and tape out custom chips end-to-end, while the company develops environments and data to teach large language models hardware workflows. The mission is to overcome the scarcity of open chip-design training data and enable more efficient, domain-specialized accelerators and broader hardware automation.
