Top Tech Jobs & Startup Jobs

Lead RTL micro-architecture and implementation of ultra-low-power communication SoC blocks. Perform RTL linting, simulation, CDC/DRC checks, gate-level simulations, MBIST/DFT integration, ECOs, and power-aware verification using UPF and VCS-NLP. Collaborate with architects, analog teams, and handle timing closure and hardmacro integration.

Lead end-to-end analog/mixed-signal IC design from specification to tapeout, drive circuit innovation to meet power/performance/area goals, collaborate with digital/layout/product teams, recruit and mentor engineers, own technical decision-making, and oversee board-level bring-up, test automation, and PCB design for production at scale.

Plan and execute end-to-end RTL verification for SoCs and IPs using SystemVerilog and UVM. Build testbenches with functional coverage and assertions, perform gate-level and power-aware verification, debug waveforms, script automation, and collaborate with design, architecture, and system teams to deliver silicon.

Perform RTL integration of IPs and subsystems into top-level SoCs, develop RTL wrappers, interconnect, clock/reset infrastructures; run lint/CDC/early synthesis checks; debug simulation and synthesis issues; automate and maintain integration flows with Python/Perl/Tcl; collaborate with design, verification, and physical design teams and contribute to design reviews and documentation.

Lead RF/analog/mixed-signal chip tapeouts from design through validation, integrate analog IPs into SoCs, prototype high-speed systems, mentor the team, validate silicon with test automation, and contribute to PCB design and firmware bring-up for wearable devices.

Lead analog and mixed-signal IP design, verification, and integration for Wi-R SoCs. Drive RF IC architecture through post-silicon bring-up, collaborate with firmware/digital/board teams, mentor junior engineers, and publish technical results. Own end-to-end chip development and long-term technical strategy for ultra-low-power wireless silicon.

Lead bare-metal bring-up of Wi-R SoCs and Cortex-M/RISC-V platforms, develop and optimize ultra-low-power firmware stacks (I2C, SPI, BLE, DMA, sensor drivers), deliver a production-ready firmware SDK, debug at register level using oscilloscopes and JTAG, mentor junior engineers, and drive toolchain and quality standards across teams.