Top Tech Jobs & Startup Jobs

Lead product definition and delivery for an AI compiler and runtime platform: own compiler/toolchain roadmap, framework integrations (PyTorch, JAX, vLLM, Hugging Face Optimum), kernel optimizations, scale-out orchestration (SLURM, Ray, LMCache), and developer UX to enable optimized execution on Majestic's Ignite APU.

Lead product strategy and execution for AI accelerator platforms, server architectures, and infrastructure products. Define PRDs, roadmaps, schedules, and release plans; coordinate silicon, hardware, software, and ops teams; prioritize features and align executive stakeholders for scalable production deployments.

Lead product strategy and execution for AI accelerator platforms, custom silicon, and server systems. Write PRDs and technical specifications, prioritize features, manage schedules and releases, and coordinate across silicon, hardware, software, AI research, operations, and executive stakeholders to deliver production-scale AI infrastructure.

Lead architecture and integration of RISC-V-based compute clusters and vector engines for AI acceleration. Define ISA extensions, interconnects, memory hierarchies, scheduling, and cache utilization; collaborate with compiler, ML runtime, RTL, verification, and firmware teams; evaluate performance/power trade-offs; and specify debug, trace, and performance-monitoring features to deliver scalable, power-efficient AI SoC compute subsystems.

Design and implement high-performance kernels for AI primitives (GEMM, attention, normalization, convolution). Optimize throughput, latency, and memory hierarchy across heterogeneous compute units. Integrate kernels with Triton/PyTorch/SYCL, profile and tune with Perfetto/VTune/Tracy, prototype precision formats and stochastic rounding, and contribute micro-architecture feedback. Write reusable C++/CUDA/Triton/LLVM MLIR code.

Lead architecture and integration of RISC-V-based AI compute clusters and vector engines. Define ISA extensions, memory subsystems, interconnects, task-mapping and scheduling, and performance/debug features. Collaborate with compiler, ML runtime, RTL, verification, and firmware teams to optimize performance-per-watt and scalability across silicon generations.

Perform chip-level and performance verification of custom ASICs. Design end-to-end test flows and methodologies with architects to verify real-world performance. Use simulation tools and UVM environments, implement constrained-random and coverage-driven tests, and collaborate across teams and vendors to validate silicon.

Lead architecture and integration of the SoC management subsystem: ARM core integration, PCIe and memory interfaces, peripherals, debug/trace, control paths, and cross-team co-design to meet performance, power, and area targets.

Design and validate modular electromechanical chassis and rack-level systems for data centers (HPC/AI/Enterprise). Own product lifecycle through high-volume manufacturing, perform thermal/structural/vibration analysis using FEA, specify metal fabrication and liquid/power connector integration, and align across silicon, power, and optical teams.

Design, develop, and optimize embedded software for AI-enabled devices. Integrate AI algorithms with hardware, improve system performance, validate and test AI features, document designs, maintain version control, and support deployment and troubleshooting of embedded AI systems.