Top Tech Jobs & Startup Jobs

2 Months AgoSaved
Hybrid
Ra'anana, ISR
Senior level
Senior level
Semiconductor • Manufacturing
Design and develop Ceva's open-source toolchain and graph compiler for DSP and NPU targets. Drive graph compilation flows, code generation, and optimizations. Integrate AI coding agents, own complex components end-to-end, mentor engineers, and collaborate with hardware, algorithm, and software teams globally.
Top Skills: C++
Reposted 2 Months AgoSaved
Hybrid
Belgrade, Grad Beograd, Centralna Srbija, SRB
Senior level
Senior level
Semiconductor • Manufacturing
Design and implement Ceva's AI Graph Compiler software stack for NPUs, optimizing performance and collaborating on hardware-software co-design while mentoring junior engineers.
Top Skills: C/C++Python
2 Months AgoSaved
Hybrid
Ra'anana, ISR
Senior level
Senior level
Semiconductor • Manufacturing
Define and optimize system and PHY architecture for advanced wireless modem products. Collaborate with algorithm, HW/SW, RF and validation teams through design, integration, testing, and customer support, with focus on low-power implementations and productization.
Top Skills: 5G Cellular IotBluetoothEmbedded SoftwareLow-Power ArchitecturemacOSMimoModemOfdmOfdmaPhy (Rx/Tx)RfSignal ProcessingUwbWi-Fi
Reposted 2 Months AgoSaved
Hybrid
Sophia Antipolis, Alpes-Maritimes, Provence-Alpes-Côte d'Azur, FRA
Senior level
Senior level
Semiconductor • Manufacturing
Lead architecture, design and verification of Bluetooth and 802.15.4 MAC/PHY and SoC subsystems. Implement digital designs on FPGA for prototyping, support validation and certification, mentor engineers, track project progress, produce subsystem documentation, and drive process and tooling improvements.
Top Skills: 3Gpp5G Cellular Iot802.15.4BluetoothCo-SimulationCode CoverageFpgaRtlSocSynthesisSystemverilogTestbenchUwbVerilogWi-Fi 802.11
Reposted 2 Months AgoSaved
Hybrid
Belgrade, Grad Beograd, Centralna Srbija, SRB
Senior level
Senior level
Semiconductor • Manufacturing
Lead development of full VLSI verification flows for DSP ASICs: define verification strategy, micro-architecture tests, test plans, functional coverage, and build SystemVerilog-UVM/Specman environments. Use formal verification and emulation, collaborate across teams, and present results to management.
Top Skills: 5G ProtocolsC++DspEmulationFormal VerificationSpecmanSystemcSystemverilog-UvmVmanagerVplan
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