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Supports and expands CMOS image sensor sales across European medical and emerging markets. Manages customer relationships, design-in activities, negotiations, forecasting, opportunity tracking, and contracts. Collaborates with marketing, business development, and field application engineering teams during technical evaluations and design cycles. Identifies new applications, gathers competitive intelligence, prepares sales reports, and attends trade shows, workshops, demonstrations, and customer meetings across Europe.

Drive automotive CMOS image sensor sales across Europe, managing strategic relationships with Tier 1 suppliers and OEMs. Lead design-in activities, negotiations, forecasting, account planning, and complete sales cycles through production ramp. Develop opportunities in robotics, security, industrial vision, and emerging imaging markets. Collaborate with marketing, engineering, product, quality, and operations teams while influencing customer technology roadmaps and supporting technical reviews, executive meetings, conferences, and demonstrations. Extensive travel throughout Europe is required.

Develop and ramp CMOS image sensor and ASIC products from tape-out through mass production. Collaborate with design, test, reliability, packaging, foundry, and quality teams on product validation, characterization, yield improvement, process optimization, failure analysis, testing programs, and customer issue resolution. Analyze wafer- and chip-level electrical data, define production specifications, support automotive compliance, and drive continuous improvement throughout the product lifecycle.

Verifies new image sensors, evaluates and tunes image quality, identifies technical solutions, and creates sensor documentation including datasheets, application notes, and reference designs. Provides accurate application guidance, directs customer support, assists field application engineers, and helps customers bring up and troubleshoot hardware, firmware, and software systems.

Designs, implements, maintains, and supports information security tools and platforms protecting systems, networks, and data. Performs security engineering, operations, vulnerability management, incident management, threat intelligence, threat hunting, and cyber threat analytics. Manages EDR, DLP, web proxy, messaging, vulnerability management, and identity-access tools; develops playbooks and troubleshooting documentation; and assists with incident response while collaborating cross-functionally to improve security posture.

Design and verify digital image sensor and SoC systems, including RTL, IP integration, ISP datapaths, high-speed interfaces, ASIC implementation, and full-chip validation. Perform simulation, synthesis, formal verification, timing analysis, DFT, FPGA prototyping, chip bring-up, silicon debugging, and performance tuning. Develop verification environments using SystemVerilog, SVA, Python, and Perl while collaborating across hardware, software, sensor, analog, and algorithm teams.

Design and develop NPU microarchitectures from system requirements, including RTL coding in Verilog/SystemVerilog, performance modeling, and PPA optimization. Collaborate with verification, software, compiler, and toolchain teams; resolve lint, timing, CDC, and integration issues; support testing and debugging; and produce design documentation. The role requires completed NPU design experience, substantial digital and SoC design expertise, and may involve leading a small engineering team.

Lead enterprise IT infrastructure automation across hybrid cloud and on-premises environments. Design automation for provisioning, software deployment, self-service workflows, and integrations with Microsoft 365, Azure, Entra, Intune, Exchange, Teams, and SharePoint. Administer Active Directory, DNS, GPOs, Windows Server, virtualization, and storage platforms. Lead global automation projects, create dashboards, maintain documentation, and participate in rotating 24/7 on-call support.

Designs, integrates, validates, and debugs digital ASIC cores and data pipelines for image sensor SoCs. Responsibilities include RTL and microarchitecture design, timing analysis, synthesis, DFT, formal verification, mixed-signal integration, chip bring-up, silicon validation, and hardware/software co-simulation. Collaborates with physical design, analog, digital, algorithm, and application engineering teams on full-chip integration, tapeout, and performance improvements.

Designs and verifies digital ASIC IP for CIS, defines chip architecture and specifications, performs synthesis, timing analysis, floor-planning collaboration, DFT, integration, and full-chip verification. The role includes silicon bring-up, validation, debug, design-flow improvement, project tracking, and mentoring junior engineers. Candidates need an MSEE and at least seven years of digital design experience, with expertise across the ASIC development lifecycle. Technical leadership, ASIL, DFT, and DSP experience are preferred.