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Implements camera ISP algorithms in hardware using Verilog, SystemVerilog, or SystemC; defines ISP architecture based on product and performance requirements; estimates gate count and power; verifies logic at ISP and digital-system levels; optimizes designs for power and area; and coordinates with algorithm, design, and system teams.

Design and verify RTL using Verilog and SystemVerilog; define system and block architectures; develop sensor timing controls and image signal processing blocks; optimize designs for low power; perform synthesis, formal verification, STA, and DFT; support silicon bring-up and production. Collaborate with analog engineers and provide technical leadership across digital silicon development.

Design and integrate digital circuit logic for image sensor and ISP systems. Responsibilities include chip architecture, RTL implementation, ISP data-path integration, PPA optimization, physical design collaboration, verification, chip bring-up, silicon debugging, and image quality tuning. The role works closely with sensor, algorithm, application, and physical design teams to achieve production readiness.

Designs transistor-level analog and mixed-signal circuits for CMOS image sensors, including block and whole-chip simulation, layout optimization, verification, debugging, characterization, and performance improvement. Collaborates with verification, process, test, and applications teams to bring image sensor products from concept through release. Conducts circuit R&D, proposes technical solutions, and guides less experienced engineers.

Develop advanced CMOS image sensor technologies and lead projects from new technology introduction through risk mass production. Optimize pixel layouts with design and TCAD teams, establish fab process conditions and experiment splits, and analyze pixel device, circuit, characterization, yield, qualification, and image-related issues. Requires semiconductor process integration expertise, project leadership, and business-level English and Japanese.

Optimize pixel structures and semiconductor fabrication processes, develop and validate CIS simulation methodologies, and model devices and systems for imaging and display technologies. The role collaborates with process integration, design, system engineering, and architecture teams to advance pixel architectures, sensors, and displays, including phase detection, dual-pixel detection, near-infrared, time-of-flight, and LCOS applications.

Support and enhance full-cycle analog and digital chip design EDA flows, automate unified design processes, and collaborate with global CAD teams. Resolve CAD issues with product developers while improving tool productivity and usability. The role requires RTL2GDS flow development, Virtuoso, Calibre, timing closure, scripting, and EDA support experience across design teams. People management experience is preferred, along with strong independent, collaborative, and English and Japanese communication skills.

Designs characterization and testing plans for CMOS imaging sensors and ASIC products, collaborating with R&D, manufacturing, foundry, testing, and pixel design teams. Improves wafer yield, silicon processes, color, packaging, layouts, and product performance through data analysis and corrective actions. Supports product definition, datasheet finalization, tape-out process flows, fab ramp-up, vendor optimization, and production testing. Uses Python to improve data-analysis efficiency.

Designs and verifies image sensor processing functions, high-speed USB and MIPI interfaces, and full-chip SoC integrations. Performs chip bring-up, validation, debugging, FPGA development, and architecture and interface documentation. Requires digital design flow experience, including Verilog RTL coding, simulation, synthesis, static timing analysis, and formality. Familiarity with FPGA and emulation platforms, SoC architecture, high-performance and low-power techniques, and formal verification is desired.

Designs and architects digital SoC platforms for video processing, neural processing, and camera analytics. Responsibilities include defining SoC architectures, developing RTL in Verilog/SystemVerilog, measuring power, timing, and area, and supporting comprehensive verification through successful silicon implementation. The role also involves processor-system integration, embedded C and assembly programming, scripting, system modeling, simulation, and cross-functional collaboration.