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Lead EDA tools and DevOps systems for ASIC chip design at Tensordyne, focusing on enhancing EDA workflows and technical support for a global engineering team.

Design, build, and optimize multi-hop data center fabrics for large-scale AI inference. Work across userspace, kernel, drivers, ASIC SDKs, firmware, and optics to tune latency, bandwidth, and reliability. Lead fabric bring-up, telemetry, automation, validation, and operational best practices while mentoring teammates and partnering with hardware, platform, and manufacturing teams.

Lead ASIC architecture definition and design for AI processors, focusing on high-performance compute and generative AI solutions. Oversee design processes and mentor teams, ensuring functionality and performance standards.