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Designs high-performance AI ASICs, including microarchitecture specifications, complex RTL, CPU and third-party IP integration, and low-power implementations. Collaborates with physical design and verification teams on timing, power, coverage closure, and implementation issues. Performs diagnostic and post-silicon validation and supports software bring-up in the lab. The role also contributes to specification reviews, vendor engagement, and exploration of accelerator architectures for AI workloads.

Lead design and development of system-level services, diagnostics, and tooling for an AI inference platform. Support board/firmware bring-up, kernel and driver development, hardware/software co-design, manufacturing test integration, and system-level performance and power optimization. Collaborate with silicon, hardware, and manufacturing teams to debug and validate platform software.

Lead ASIC verification for next-gen processors in AI inference. Oversee full verification cycle, mentor engineers, and establish methodologies.

The role involves leading the development of AI inference compute products, engaging with partners and customers, and managing product strategies and performance metrics.

The Sr. Staff Hardware Design Engineer will oversee hardware system engineering for AI products, handle schematic capture and PCB design, and coordinate with teams for product compliance and validation.

Drive adoption of AI inference platform across large enterprises, own sales cycle, lead technical evaluations, engage executive stakeholders, and shape GTM strategy.

Develop and implement manufacturing test solutions for high-performance AI servers, focusing on automated testing, collaboration with teams, and debug analysis.

The Hardware Design Engineer will oversee hardware system development including schematics, PCB layout, and component selection while collaborating with various teams for product testing and validation.

Responsible for Design Verification Testing and sustaining of new hardware products, including creating test plans, debugging, and ensuring performance specifications are met.

Lead EDA tools and DevOps systems for ASIC chip design at Tensordyne, focusing on enhancing EDA workflows and technical support for a global engineering team.