About our company - Tensordyne (formerly Recogni)
Artificial intelligence (AI) is transforming our world. It can perform cognitive functions that previously only humans could do, such as perceiving interactions across different modalities and environments - with the ability to quickly learn and then solve complex problems. Tensordyne is an AI system solution company that builds very high-performance, low-power generative AI inference systems. Our mission, through the creation of custom silicon, hardware and software, is to enable multimodal Generative AI inference acceleration at scale, with safe, sustainable, high-performance systems for our hyperscaler and neocloud data center customers. We are at the leading edge of advancing the latest research and product improvements for generative Al inference solutions that will make Al even more advantageous for compelling new generative AI applications.Tensordyne is a well funded, fast-paced startup company with headquarters in both Sunnyvale, CA, and Munich, Germany. We also have many talented team members working remotely across North America and Europe. We take care of our people and their families with comprehensive benefits, competitive compensation, flexible spending options, and recognition programs, because building category-defining technology starts with a healthy, supported team. Come join us as we shape the future of multimodal generative artificial intelligence!
The Opportunity:
In this leadership role, you will lead ASIC front-end physical design and associated engineering workflow development for Tensordyne’s multimodal generative AI inference acceleration products. As a valued senior member of our ASIC team, you will guide and assist your colleagues to help improve frontend physical design aspects at both the block level and full-chip within a fast-paced, agile HPC development environment that utilizes EDA tools from external companies like Cadence/Synopsys and as well as internally developed workflows. You will drive Tensordyne’s optimization, implementation and exploration of new frontend physical design workflows (includes at a min. synthesis, formal checks, and power analysis, and provide guidance for STA) and technologies for the full ASIC chip design process. Your contributions will continuously innovate and improve scalable, reliable, high-performance systems and tools to enable the next generation of Tensordyne products. This is a hands-on role that’s ideal for ASIC physical design experts who have a multi-disciplinary engineering background, along with a keen interest in generative AI, and a passion for designing, debugging, optimizing and finding creative EDA solutions to complex technical challenges. In this role, you will work very closely with your ASIC team members who are engaged in the design and verification of Tensordyne products, to understand and improve their workflows and EDA needs.
What you’ll bring:
- 10+ years of hands-on ASIC engineering experience, that includes deep knowledge of VLSI/SoC chip physical design workflows, with EDA tools like Cadence/Synopsys (Genus/DC), power analysis, clock methodology, and other commonly used aspects of physical design flows
- Strong physical design knowledge for front-end optimization using standard EDA tools
- Experience leading and supporting backend design team with understanding of clock trees, routing , DRC, LVS, metal fill till artwork release.
- Understanding of STA analysis and constraints for block level and knowledge of full chip timing analysis
- Excellent analytical, written, and verbal interpersonal skills along with an ability to productively collaborate within a global engineering team that moves at a startup pace.
- Bachelor’s or Master's degree in Computer Science, Computer Engineering, Electrical Engineering or a related technical field
Tensordyne's culture was built on the following values:
- Put people first. We only succeed when our people succeed.
- Ethics and integrity always; Being open, honest, and respectful of everyone.
- Think Big. Be ambitious and have audacious goals.
- Aim for excellence. Quality and excellence count in everything we do.
- Own it and get it done. Results matter!
- Make each person better together, than they would be as an individual.
- Embrace each others’ differences, and embrace that there will be differences.
Tensordyne is an equal opportunity employer. We believe that a diverse team is better at tackling complex problems and coming up with innovative solutions. All qualified applicants will receive consideration for employment without regard to age, color, gender identity or expression, marital status, national origin, disability, protected veteran status, race, religion, pregnancy, sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances.
A note to Recruitment Agencies: Please don’t reach out to Tensordyne employees or leaders about our roles -- we’ve got it covered. We don’t accept unsolicited agency resumes and we are not responsible for any fees related to unsolicited resumes. Thank you for your understanding.
Skills Required
- 10+ years of hands-on ASIC engineering experience
- Deep knowledge of VLSI and SoC physical design workflows
- Experience with Cadence and Synopsys EDA tools, including Genus and Design Compiler
- Experience with power analysis and clock methodology
- Strong ASIC front-end physical design optimization knowledge
- Experience leading or supporting backend design teams
- Understanding of clock trees, routing, DRC, LVS, metal fill, and artwork release
- Understanding of block-level STA and full-chip timing analysis
- Excellent analytical, written, verbal, and interpersonal skills
- Ability to collaborate within a global engineering team
- Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field
What We Do
Every leap in AI has followed the same pattern: first we made models bigger, then we tailored them, and now we let them think longer. Each step (scaling law) truly adds intelligence. But in the end we land on the same runway: inference, and demand is exploding while power supply lags. We asked: what if the next step isn’t stacking another law on top, but a zeroth law beneath them all. A law that changes AI math. Because after all, AI is math, trillions of multiplies, and multiplication burns watts. Tensordyne uses logarithmic compute to turn multiplies into adds, cutting power at the root. We’ve cast our proprietary logarithmic math into custom silicon, hardware, interconnect, and system software. The result: one integrated system for multimodal GenAI inference designed for Hyperscaler and Neo Cloud data centers. What this means for our customers: With Tensordyne they can run the world’s largest multimodal models for thousands of users, with fewer racks, less power, and lower cost. We’re well-funded and fast-moving, with co-headquarters in Sunnyvale, California and Munich, Germany, and a distributed team across North America and Europe. Join us to change how the world runs Gen AI.
