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Own and improve wafer-level testing operations, including process development, qualification, production execution, process control, yield improvement, failure debugging, data analysis, documentation, and cycle-time optimization. Lead continuous improvement using DOE, SPC, Six Sigma, and root-cause analysis while collaborating with engineering, quality, supply chain, and manufacturing partners to support product qualification and production ramp.

Lead development, integration, optimization, and technical support for wafer bumping and Fan-Out processes used in silicon photonic chip wafers. Responsibilities include process pathfinding, materials qualification, reliability validation, failure analysis, yield improvement, SPC control, incoming wafer quality, and NPI documentation. The role requires hands-on advanced packaging experience and expertise in photolithography, deposition, electroplating, finite element analysis, DOE, FMEA, and analytical software.

Lead full-custom analog and mixed-signal layout for advanced CMOS silicon platforms, including PLLs, converters, regulators, and high-speed I/O. Define layout methodologies, drive parasitic-aware implementation, own DRC/LVS and physical verification closure, and support tape-out readiness. Collaborate with circuit, physical design, process technology, and design kit teams on floorplanning, PDK qualification, and post-layout analysis. Mentor engineers and coordinate contractors while establishing scalable physical design roadmaps across silicon programs.

Provides L1/L2 desktop support for Windows and macOS, including device provisioning, troubleshooting, patching, onboarding, offboarding, asset management, and peripheral support. Assists with LAN, Wi-Fi, VPN, switching, and wireless access point operations. Administers Microsoft 365 and Entra ID accounts, licenses, groups, devices, compliance policies, MFA, and endpoint applications. Supports Intune, Azure, ITSM tools, security platforms, and basic PowerShell automation while coordinating escalations and maintaining technical documentation.

Provides first-line T1 and T2 helpdesk support across macOS, Windows, and Linux. Responsibilities include ticket triage, device imaging and deployment, onboarding and offboarding, identity administration, connectivity troubleshooting, hardware asset management, conference room AV support, and maintaining IT documentation. The intern will also collaborate on endpoint management, SaaS administration, identity access management, and security initiatives.

Build and own data pipelines, models, quality checks, dashboards, and visualizations for manufacturing and test data. Partner with optical, manufacturing, and quality engineers to create reliable data solutions, improve pipeline performance and cost, and support engineering and leadership decisions. Establish software engineering practices for data systems, guide technical direction across distributed sites, and mentor other engineers.

Owns strategy and execution for high-speed optical interconnect product lines, including co-packaged optics, 800G, and 1.6T transceiver platforms. Coordinates engineering, manufacturing, suppliers, quality, supply chain, sales, finance, and operations to drive product development, validation, launch readiness, customer adoption, and production transfer. Responsibilities include market and competitive analysis, customer engagement, technical trade-off evaluation, roadmap execution, risk management, business cases, and leadership reporting.

Lead development of packaged silicon photonics and optical interconnect products from requirements through validation and production. Define product requirements, analyze optical links, coordinate engineering and external partners, guide packaging and assembly execution, and establish testing strategies. The role requires hands-on laboratory work, customer and supplier engagement, cross-functional leadership, and attention to manufacturability, reliability, thermal performance, and scale-up readiness.

Support strategy, execution, adoption, and lifecycle management for high-speed optical interconnect product lines. Analyze customer and market requirements, competitive intelligence, technical trade-offs, and business metrics for 800G and 1.6T transceiver platforms. Coordinate with engineering, sales, manufacturing, finance, operations, and customer teams to resolve issues, support design wins, execute roadmaps, identify risks, and develop customer proposals and business cases.

The Director of Silicon Test Engineering will lead test strategy and execution for silicon photonics products, optimizing test solutions and ensuring product reliability. Responsibilities include managing ATE test development, driving yield optimization, and collaborating with cross-functional teams while building a high-performing engineering team.