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7 Days AgoSaved
In-Office
San Jose, CA, USA
Mid level
Mid level
Artificial Intelligence • Machine Learning • Database • Manufacturing
Develops and executes UVM-based functional verification for chiplet blocks and subsystems. Responsibilities include building testbenches, writing constrained-random tests, achieving coverage closure, integrating VIP, debugging regressions, verifying firmware and mixed-signal models, and supporting emulation, FPGA prototyping, gate-level, and low-power verification. The role collaborates with design, architecture, modeling, and DFT teams through signoff.
Top Skills: AsicCi/Regression FlowsCxlEthernetFormal VerificationFpgaHapsPalladiumPam4PciePerlPortable StimulusProtiumPythonReed-SolomonSerdesSocSystemverilogSystemverilog Real-Number ModelsTclUalinkUcieUpfUvmVeloceVerilog-Ams
7 Days AgoSaved
Hybrid
2 Locations
Senior level
Senior level
Artificial Intelligence • Machine Learning • Database • Manufacturing
Develop C#/.NET desktop manufacturing software for optical transceiver testing. Build WPF/MVVM interfaces, concurrent test execution, hardware drivers, instrument resource management, RPC services, and embedded Python testing capabilities. Design reliable, testable systems using clean architecture, MongoDB, GitHub Actions, and automated deployment to Windows machines. Diagnose distributed failures through logs and telemetry while supporting software operating at manufacturing scale.
Top Skills: .Net 8BashC#Ci/CdGitGithub ActionsGpibI2CMesMongoDBMstestMvvmPowershellPytestPythonRpcScpiSerial CommunicationTcp SocketsVisaWpfXunit
7 Days AgoSaved
In-Office
San Jose, CA, USA
Expert/Leader
Expert/Leader
Artificial Intelligence • Machine Learning • Database • Manufacturing
Leads end-to-end design verification for a photonics chiplet, defining verification strategy, UVM architecture, coverage, signoff, regressions, emulation, FPGA prototyping, UCIe compliance, mixed-signal co-simulation, low-power and gate-level verification. Owns performance validation, firmware and boot-flow verification, and grows a cross-functional DV team across FEC, UCIe, MCU, datapath, and full-chip domains.
Top Skills: AsicCi/CdCode CoverageConstrained-Random VerificationCxlEthernetFirmware Co-SimulationFormal VerificationFpga PrototypingFunctional CoverageGate-Level SimulationHapsPalladiumPam4PciePortable StimulusProtiumReed-SolomonRegression AutomationRtlSerdesSocSystemverilogSystemverilog Real ModelsUalinkUcieUcie VipUpfUvmVeloceVerilog-Ams
7 Days AgoSaved
In-Office
Bengaluru, Bengaluru Urban, Karnataka, IND
Expert/Leader
Expert/Leader
Artificial Intelligence • Machine Learning • Database • Manufacturing
Own end-to-end design verification for a photonics chiplet, defining verification strategy, coverage, UVM architecture, regressions, emulation, FPGA prototyping, mixed-signal co-simulation, UCIe compliance, performance validation, gate-level and low-power signoff. Lead and grow a distributed DV team while driving verification across FEC, interconnect, MCU, datapath, and full-chip systems through tapeout.
Top Skills: Ci/CdCxlEthernetFormal VerificationFpgaHapsPalladiumPciePortable StimulusProtiumSystemverilogUalinkUcieUpfUvmVeloceVerilog-Ams
7 Days AgoSaved
In-Office
San Jose, CA, USA
Senior level
Senior level
Artificial Intelligence • Machine Learning • Database • Manufacturing
Designs high-speed analog and MMIC circuits for photonic interconnects from architecture through tapeout and silicon validation. Responsibilities include schematic design, EM modeling, parasitic extraction, simulation, physical verification, reliability signoff, automation scripting, layout collaboration, and lab characterization. Requires advanced analog IC design expertise, high-frequency analysis, EDA proficiency, and experience with advanced process technologies.
Top Skills: BertsCadence EmxCadence SkillCadence Virtuoso StudioCalibreCmosEm/IrPerlPrimesimQuantus QrcSampling OscilloscopesSige BicmosSignal IntegritySpectreSynopsys HspiceTransmission-Line ModelingUnix ShellVnasVoltus-Xfi
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14 Days AgoSaved
In-Office
Singapore, SGP
Mid level
Mid level
Artificial Intelligence • Machine Learning • Database • Manufacturing
Manage reception, office administration, facilities, supplies, vendors, purchasing, expenses, confidential records, events, travel, and executive support. Ensure smooth daily office operations, maintain shared spaces, coordinate maintenance and service providers, handle calls and visitors, and support meetings and team activities. The role requires strong organization, discretion, communication in English and Chinese, multitasking, and proactive problem-solving in a fast-paced startup environment.
20 Days AgoSaved
In-Office
Kulim Square, Keladi, Kulim, Kedah, MYS
Senior level
Senior level
Artificial Intelligence • Machine Learning • Database • Manufacturing
Manages the manufacturing site’s front desk and daily administration. Responsibilities include visitor and contractor access, mail and deliveries, office and facility coordination, inventory, vendor services, HR onboarding logistics, purchasing, expenses, customer and supplier visits, and travel arrangements. The role is fully onsite and requires discretion, strong organization, communication skills, and experience supporting office operations in a manufacturing or high-tech environment.
Top Skills: Erp SystemsMS OfficePurchasing SystemsVisitor Management Systems
Reposted 20 Days AgoSaved
In-Office
Singapore, SGP
Senior level
Senior level
Artificial Intelligence • Machine Learning • Database • Manufacturing
Lead development and optimization of wafer backside grinding, laser stealth dicing, and die sorting for silicon photonics. Troubleshoot process issues, improve yield and throughput, ensure compatibility with bumping/flip-chip, and produce SOPs, WIs, failure reports, and support NPI and process verification.
Top Skills: Bump (Bumping)Die SortingDoeFlip-ChipJmpLaser Stealth DicingSpcWafer Backside GrindingWafer DicingWafer Thinning
26 Days AgoSaved
In-Office
Bengaluru, Bengaluru Urban, Karnataka, IND
Senior level
Senior level
Artificial Intelligence • Machine Learning • Database • Manufacturing
Design and implement complex analog, mixed-signal, RF, and connectivity IP layouts from floorplanning through tapeout. Responsibilities include physical verification and signoff using DRC, LVS, ERC, antenna, DFM, and EMIR; optimizing layouts based on extraction results; collaborating with circuit, verification, CAD, and technology teams; and improving productivity through automation, scripting, and AI-assisted workflows.
Top Skills: Ai-Assisted WorkflowsBicmosCadence VirtuosoCmosDfmDrcEda ToolsEmirErcEsd ProtectionFinfetLvsRc ExtractionScriptingSige
One Month AgoSaved
In-Office
Singapore, SGP
Expert/Leader
Expert/Leader
Artificial Intelligence • Machine Learning • Database • Manufacturing
Design, manage, secure, and optimize Lumilens’s global multi-site LAN, WAN, SD-WAN, VPN, cloud, wireless, and enterprise network infrastructure across India, Thailand, Singapore, and the US. Responsibilities include firewall and network device administration, SASE and Zero Trust deployments, Azure and Microsoft 365 integration, identity-aware access, monitoring, automation, vendor evaluation, documentation, and collaboration with distributed teams.
Top Skills: ArubaAzure VnetBashBgpCato NetworksCiscoEnterprise Wi-FiEntra IdExchange OnlineExpressrouteFortigateFortinetGrafanaIpsecIptablesJuniperLagLinuxMerakiMicrosoft 365NatNetsuite ErpOidcOspfPalo AltoPfsensePowershellPrtgPythonSAMLSaseSd-WanSharepointSolarwindsSsl-VpnStpTeamsVlanZabbix
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