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Lead backend physical implementation from netlist to GDSII: floorplanning, placement, CTS, routing, ECOs, sign-off, PPA optimization, power and signal integrity analysis, FPGA-specific integration, EDA tool and flow development (Tcl/Python/Perl), manufacturing/package integration, debugging, and mentoring junior engineers.

Provide internal sales support for assigned accounts across lead-to-order and order-to-cash processes: manage orders, forecasts, pricing/quotes, escalations, CRM data, NPI/sample coordination, and prepare sales reports and QBR materials while collaborating cross-functionally.

12-month interim Internal Sales Representative supporting field sales and FAEs. Manage Lead-to-Order and Order-to-Cash processes, customer account management, order management, pricing/quote requests, escalations, distributor coordination, demand collection and sales forecasting, CRM data maintenance, NPI/sample coordination, sales reporting, and onboarding support.

Lead SOC and block-level physical implementation from floorplan and power intent through final signoff. Drive STA, power integrity, PPA optimization, and physical verification. Integrate and productize ML/AI optimization into PnR flows. Mentor a team of physical designers, lead cross-functional convergence, define methodology and constraints (SDC/UPF), and represent physical design in architecture and tapeout planning.

Lead physical implementation of custom IP and SoC from RTL through GDSII. Execute synthesis, floorplanning, place-and-route, CTS, STA, power, reliability and physical verification. Analyze signoff results, resolve violations, optimize PPA, and develop/automate physical design methodologies while collaborating with RTL, DFT, timing, verification, and CAD teams.

Implement full-chip and block-level physical design for custom IP and SoC from RTL through GDSII. Execute synthesis, floorplanning, place-and-route, CTS, STA, physical verification and signoff. Optimize power, timing, congestion, and PPA, support DFT integration, root-cause issues, automate flows, and mentor junior engineers across multidisciplinary teams.

Lead the design and development of FPGA-centric solutions for robotics and industrial automation, while mentoring a skilled engineering team and engaging with customers.

The Junior Logic Design Engineer will assist in logic design and RTL development, support architectural discussions, and collaborate on verification activities while gaining hands-on experience in a team environment.

Responsible for verifying Design for Debug architecture, creating test cases and test benches using UVM. Coordinate cross-functional efforts for full coverage verification.

Lead DFT architecture and strategy, oversee complex DFT implementation, ensure sign-off quality, and mentor engineers. Drive collaboration across multiple teams, optimize power and timing, and provide leadership in functional safety and quality efforts.