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The High Level Synthesis Compiler Engineer will develop and optimize compilers, mentor engineers, and support customers in achieving design goals in FPGA design.

Develop and maintain HLS compiler infrastructure, implement compiler passes and code transformations, optimize C/C++ to hardware flows, research compiler techniques for AI workloads, integrate and test HLS features, debug and validate compiler outputs, and document work for knowledge sharing.

Consult on and optimize Workday Recruiting and Learning processes globally: streamline workflows, increase recruiter efficiency, improve onboarding and learning administration, build dashboards and analytics, identify automation/AI opportunities, and partner with HR, TA, and business leaders to implement scalable Workday solutions and a long-term optimization roadmap.

Design, implement, and debug FPGA-based prototypes for ASIC validation and prototyping. Develop RTL in Verilog/SystemVerilog, integrate high-speed IPs (PCIe, DDR/LPDDR, Ethernet, CXL, HBM), perform synthesis/place-and-route/timing closure, and create automation scripts. Collaborate with architecture, verification, firmware, and post-silicon teams to resolve functional and performance issues and improve FPGA methodology and bring-up plans.

Design, implement, and optimize FPGA placement algorithms to improve timing, congestion, resource utilization, and runtime for large designs. Integrate placement into the compiler flow, collaborate with routing, synthesis, architecture, and timing teams, analyze convergence and QoR, and validate toolchain performance across diverse workloads.

Architect, implement, and optimize FPGA-based signal processing and embedded computing solutions for aerospace and defense. Work with customers and internal teams to deploy DSP, communications, and AI algorithms on FPGA devices; develop benchmarks, reference designs, and documentation; analyze and tune system performance for throughput, latency, power, and resource utilization; support debugging, performance tuning, and technical enablement.

Own and reconcile fixed asset and related general ledger accounts (PPE, CIP/AUC, prepaids, AP, accruals). Prepare roll-forwards, journal entries, physical count coordination, capitalization reviews, SOX controls support, audits, and ERP/fixed-asset process improvements.

Manage monthly close and GL for prepaids, AP, accruals, liabilities, and PPE. Lead reconciliations, journal entries, roll-forwards, variance analysis, SOX controls, and audit support. Review IT/R&D contracts for accounting treatment, improve processes and systems, and coordinate U.S. and international accounting teams.

Lead emulation strategy and implement emulation methodologies for pre-silicon validation. Develop and debug emulation testbenches for complex FPGA designs, integrate hardware and software, build automation frameworks, identify performance bottlenecks, and improve emulation infrastructure while collaborating with silicon design, verification, and firmware teams.

Perform block-level physical implementation of custom IP and SoC designs from RTL to GDSII. Execute synthesis, floorplanning, P&R, CTS, STA, and physical verification. Resolve timing, power, and signal-integrity issues, support DFT integration and signoff, and develop/automate physical design methodologies to optimize PPA and manufacturability.