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Lead emulation strategy and implement emulation methodologies for pre-silicon validation. Develop and debug emulation testbenches for complex FPGA designs, integrate hardware and software, build automation frameworks, identify performance bottlenecks, and improve emulation infrastructure while collaborating with silicon design, verification, and firmware teams.

Perform block-level physical implementation of custom IP and SoC designs from RTL to GDSII. Execute synthesis, floorplanning, P&R, CTS, STA, and physical verification. Resolve timing, power, and signal-integrity issues, support DFT integration and signoff, and develop/automate physical design methodologies to optimize PPA and manufacturability.

We are looking for a college graduate to design and optimize layout for analog and mixed-signal integrated circuits, collaborating with experienced engineers on various tasks.

The Treasury Manager will oversee cash flow forecasting, manage global bank accounts, ensure compliance, and lead automation projects in the treasury department.

The Internal Sales Representative supports field sales by managing customer relationships, processing orders, coordinating with cross-functional teams, and preparing sales reports.

Develop and validate testability and manufacturability for integrated circuits from feasibility through production ramp. Create and debug test circuits, ATE test flows, validation and production test hardware, and software to drive test equipment. Perform ATE characterization, yield and bin-split analysis, collaborate with fab/assembly/test teams to resolve post-silicon issues, drive manufacturing readiness, and optimize test time and cost for high-volume manufacturing.

Lead RTL-to-GDSII implementation for multiple design partitions, manage end-to-end physical design flow (synthesis-like, floorplanning, placement, custom pre-route), achieve timing closure and physical signoff, perform IR/RV, FEV, LVS/DRC checks, collaborate with custom macro teams, and resolve timing, congestion, and power issues independently.

Responsible for design validation of high-speed protocol IPs, creating verification plans, developing testbenches, and collaborating with teams for implementation and quality improvement.

The DFX Design Architect will lead strategy on DFT and DFD for high-performance FPGA designs, ensuring quality, cost optimization, and time-efficient design processes while mentoring engineering teams.

Lead end-to-end hardware platform and PCB design for processor/FPGA/SoC systems including schematic capture, PCB layout, SI/PI/thermal simulations, BOM optimization, board bring-up, and cross-functional integration to meet performance, power, thermal, and cost objectives.