Top Tech Jobs & Startup Jobs

Develops EMEA embedded-business opportunities by building OEM, partner, and ecosystem relationships; translating FPGA and SoC requirements into solutions; leading technical workshops and proof-of-concept discussions; creating account and opportunity plans; supporting design wins and competitive displacement; and coordinating Field Sales, FAE, product, marketing, and engineering teams to drive pipeline, revenue, and long-term growth.

Lead the architecture, development, testing, and support of integrations across Blue Yonder supply chain platforms, PLM systems, Oracle Fusion ERP, and downstream Lakehouse or data warehouse environments. Build Python, SQL, ETL/ELT, and batch integrations; ensure data integrity, reconciliation, monitoring, and error handling; coordinate global stakeholders; manage integration backlogs; document data flows; and provide Tier-3 support for synchronization failures.

Supports FPGA and ASIC physical design implementation, including floorplanning, placement, clock tree synthesis, routing, timing closure, physical verification, and signoff. Analyzes timing, power, congestion, and design rule reports; assists with ECOs, debugging, automation, silicon bring-up, and post-silicon support. Collaborates with RTL, DFT, CAD, verification, and other engineering teams to optimize designs for timing, power, area, and manufacturability.

Designs and validates FPGA implementations and embedded software features for customer applications using FPGA-SoC devices. Collaborates with silicon design, CAD tools, applications engineering, and product planning teams. The role involves hands-on work with hardware, software, development kits, digital design, and programming while supporting customer-focused solutions.

Leads foundry relationships, process technology enablement, silicon manufacturing, yield improvement, reliability, and high-volume production for FPGA products. Oversees process qualification, PDK readiness, manufacturability, risk management, capacity planning, cost optimization, and supply assurance. Partners with design, product engineering, quality, supply chain, and executive teams while building and mentoring a foundry engineering organization.

Lead strategy, development, deployment, and scaling of custom-analog design automation and AI-assisted workflows. Automate schematic, layout, verification, and signoff processes; apply AI/ML to sizing, layout assistance, and verification triage; establish IP reuse and flow-hardening practices; measure productivity and adoption; partner across fabric, SerDes, and IO teams; and mentor engineers adopting new methodologies.

Lead physical design execution across blocks and full-chip integration from floorplanning through tapeout. Own schedules, quality, risk mitigation, cross-team coordination, critical-path recovery, and signoff alignment. Partner with methodology and CAD teams, resolve execution blockers, engage senior customer stakeholders, and mentor physical design engineers. The role requires hands-on expertise in advanced-node implementation, timing and power closure, signoff flows, scripting, and delivery across complex multi-site designs.

Manages financial planning and control for federal government programs, including multi-year budgets, forecasts, cost estimates, EAC reporting, contract compliance, and financial risk mitigation. Analyzes project costs, supports pricing models, reviews subcontractor invoices, tracks procurement spending, prepares audit documentation, and briefs stakeholders. Requires expertise in federal contracting regulations, financial modeling, Excel, and Oracle or SAP accounting systems.

Lead the development, modeling, verification, and validation of FPGA IP and simulation models within the Altera Quartus Prime ecosystem. Define technical direction, develop RTL and behavioral or cycle-accurate models, improve verification and regression strategies, debug simulation, fitter, and timing issues, integrate Quartus flows, automate engineering processes with Python and Tcl, and mentor engineers.

Develop and automate validation tests for FPGA device and simulation models used by Altera Quartus Prime. Build regression infrastructure, execute end-to-end synthesis, fitting, and simulation flows, maintain reference results, analyze failures, and debug issues across RTL, constraints, tools, and C++ models. Develop automation and device-model libraries using C++, Tcl, Python, and Bash; integrate validation into CI pipelines; improve coverage, quality metrics, documentation, and release readiness.