FPGA Development Tools Engineer

Posted 6 Hours Ago
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Penang, Daerah Timor Laut, Penang, MYS
In-Office
Expert/Leader
Artificial Intelligence • Internet of Things • Machine Learning
The Role
Lead the development, modeling, verification, and validation of FPGA IP and simulation models within the Altera Quartus Prime ecosystem. Define technical direction, develop RTL and behavioral or cycle-accurate models, improve verification and regression strategies, debug simulation, fitter, and timing issues, integrate Quartus flows, automate engineering processes with Python and Tcl, and mentor engineers.
Summary Generated by Built In
Job Details:

Job Description:

📌 Role Overview 

We are seeking a Senior Technical Lead to drive the development, modeling, and validation of FPGA IP and simulation models within Altera Quartus Prime ecosystem. 

This is a hands-on leadership role — you will: 

  • Define technical direction 
  • Lead complex problem-solving 
  • Actively contribute to design, modeling, and debugging 

You will play a critical role in improving IP quality, simulation accuracy, and engineering productivity, while mentoring engineers and shaping best practices. 

 

🎯 Key Responsibilities 

🔹 Technical Leadership (Hands-On) 

  • Own technical direction for IP and simulation model 
  • Lead design reviews, architecture discussions, and validation strategies 
  • Dive deep into complex issues and personally drive resolution 

 

🔹 IP Development & Modeling 

  • Design and implement FPGA IP (RTL/SystemVerilog/VHDL) 
  • Develop high-fidelity simulation models:  
    • Behavioral 
    • Cycle-accurate 
  • Ensure consistency between:  
    • Simulation models 
    • Hardware implementation 

 

🔹 Verification & Validation Strategy 

  • Define and enforce robust verification methodologies:  
    • SystemVerilog 
    • Assertion-based verification 
  • Oversee and contribute to:  
    • Testbench architecture 
    • Coverage strategy 
    • Regression systems 

 

🔹 Debug & Root Cause Leadership 

  • Lead debugging of complex issues across:  
    • Simulation 
    • Fitter 
    • Timing analysis 
  • Translate low-level issues into:  
    • Clear root cause 
    • Actionable fixes 

 

🔹 Quartus Flow Integration 

  • Ensure seamless integration with:  
    • Compilation 
    • Fitter 
    • Timing closure 
  • Identify and drive improvements in:  
    • Tool usability 
    • Debuggability (e.g., Fitter insights) 

 

🔹 Productivity & Automation 

  • Champion engineering productivity improvements:  
    • Automation frameworks (Python, Tcl) 
    • Regression infrastructure 
    • AI-assisted workflows (where applicable) 

 

🔹 Mentorship & Team Development 

  • Mentor engineers in:  
    • Debugging 
    • Design quality 
    • Verification practices 
  • Raise overall team capability in:  
    • Root cause analysis 
    • System-level thinking

Qualifications:

🧠 Required Qualifications 

  • Bachelor’s or Master’s in:  Electrical Engineering / Computer Engineering 
  • 8–12+ years of experience in:  FPGA design, IP development, or verification 
  • Strong hands-on expertise in:  RTL design (Verilog/SystemVerilog/VHDL)
  • Simulation & verification 
  • Deep experience with:  Altera Quartus Prime or equivalent FPGA toolchains 
  • Proven ability to:  Debug complex system-level issues  and Lead technical initiatives 

Job Type: Regular

Shift:Shift 1 (Malaysia)

Primary Location:Penang 15, Penang, Malaysia

Additional Locations:

Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Skills Required

  • Bachelor's or Master's degree in Electrical Engineering or Computer Engineering
  • 8-12+ years of experience in FPGA design, IP development, or verification
  • Strong hands-on expertise in RTL design using Verilog, SystemVerilog, or VHDL
  • Experience with simulation and verification
  • Deep experience with Altera Quartus Prime or equivalent FPGA toolchains
  • Ability to debug complex system-level issues
  • Ability to lead technical initiatives

Altera (altera.com) Compensation & Benefits Highlights

The following summarizes recurring compensation and benefits themes identified from responses generated by popular LLMs to common candidate questions about Altera (altera.com) and has not been reviewed or approved by Altera (altera.com).

  • Retirement Support Feedback suggests retirement programs are robust, with offerings such as a 401(k) and a pension. This breadth supports long-term financial security.
  • Leave & Time Off Breadth Feedback suggests time-off policies are generous, including PTO, paid sick days, and paid holidays. Wellness initiatives like gym memberships further support balance.
  • Parental & Family Support Feedback suggests parental leave is generous. Family-building support, including fertility benefits and adoption reimbursement, is highlighted as part of the package.

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The Company
HQ: San Jose, California
1,612 Employees
Year Founded: 1983

What We Do

Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet.

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