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Design and prototype FPGA blocks for high-speed PHY/SerDes IP and multi-Gigabit data-link transceivers. Validate and bring up devices and FPGAs in the laboratory, collaborate with firmware, digital, verification, and lab teams, and use RTL, scripting, and industry-standard FPGA tools for design validation, simulation, and verification.

Lead the signal integrity and power integrity function, guiding architecture, resolving system challenges, and collaborating on robust solutions for AI hardware.

Design and implement DFT solutions including hierarchical MBIST and scan insertion, ATPG pattern generation and coverage convergence, timing-aware pattern simulation, IJTAG cycle-accurate functional patterns, and debug silicon with test and production teams through probe and final test.

The Silicon Product Engineer will manage relationships with silicon partners, oversee silicon manufacturing processes, and enhance product quality and efficiency, while ensuring timely delivery of products in collaboration with cross-functional teams.

The Digital Design Engineer will design and verify high-speed digital circuits, manage block specifications, and support integration, validation, and customer interaction.

Develop, document, and maintain system-level models for serial communication links using MATLAB, Python, and C++. Collaborate with system, analog, digital, and verification teams to define transceiver block-level specs, budget link performance, and support design and verification activities.

Looking for circuit designers specializing in SerDes with HF frequency experience and Precision LF with DC circuit implementation at 5nm nodes.

MSc intern will research and model simultaneous bidirectional communication over wideband copper serial links: develop behavioural channel and transceiver models, study self-interference cancellation, simulate building blocks with Python or circuit CAD tools, evaluate channel impairments, and quantify achievable data rates and energy efficiency. Deliver technical report and presentation; potential publication opportunities.

Design and verify custom analog circuits for high-speed serdes transceivers, collaborating with teams and supporting customer interactions as needed.

Work with the CTO to conceive, model, and prototype next-generation chip-to-chip and die-to-die communication and interconnect architectures. Develop signaling, coding, equalization, and system-level techniques; build simulations and prototypes; evaluate performance, power, latency, area, and manufacturability tradeoffs; and translate research into silicon-ready architectures and IP while providing technical leadership across teams.