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The role involves designing communication systems as a VLSI Design Engineer, focusing on architectural challenges and implementation details, requiring 5 years of experience in ASIC/FPGA design.

Responsible for backend design implementation from RTL to GDSII, including timing closure, power management, and physical verification. Collaborate with teams and enhance P&R flows.

Responsible for end-to-end verification of RTL designs, leading test bench architecture, mentoring engineers, and ensuring full functionality through detailed coverage analysis.

The Backend Engineer will manage RTL-to-GDSII design flows, ensuring successful silicon execution, timing closure, low power design, and IP integration, collaborating closely with the design team.

The DFT Engineer will define and implement DFT methodologies for complex digital chips, debug DFT features, and validate silicon tests.

Design and lead high-speed, low-noise analog layouts (ADC/DAC) for optical-communication chips in advanced TSMC processes. Use Cadence layout tools, support tape-out procedures, collaborate with cross-functional teams, and ensure schematic-flow alignment. Mentor-tools experience preferred.