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Develop and optimize Edge AI software on NXP SoCs, deploy machine learning models to real-time embedded platforms, integrate AI inference runtimes, profile and optimize latency/memory/power, collaborate with cross-functional teams, and participate in implementation, testing, debugging, and validation.

Design and deliver analog/mixed-signal IP for MCUs: define architectures, implement, simulate (behavioral and transistor-level), perform layout and validation, guide verification and integration, document designs, and support productization including characterization and production test.

Lead STA signoff for SoC/subsystem through tapeout. Write and validate timing constraints, generate/validate SDF, drive SI closure, collaborate with Frontend/DFT/IP, apply AI to STA tasks, and define physical design strategies across advanced nodes (16nm, 5nm).

Responsible for physical implementation of IP/Subsystem/IC from RTL synthesis to GDS, including floorplanning, routing, STA timing closure, design ECOs, and physical verification to meet DRC/LVS, electromigration, and IR drop rules. Defines physical design strategy per technology node and contributes to solving physical design issues.

Lead Mass Market Technical Support for the Americas: manage and develop FAEs, align distributor technical enablement, drive design-in for microcontrollers/processors/connectivity/edge AI, collaborate cross-functionally to grow design wins, and recruit and train early-career engineers.

Lead architecture and implementation of advanced DFT strategies (scan, JTAG, MBIST/LBIST), oversee ATPG and test compression, perform pre/post-silicon verification and debug, improve test coverage and collaborate with RTL and physical teams for timing and silicon bring-up.

Responsible for developing and integrating drivers and flow during the pre-silicon stage of the chip, collaborating with design teams and external vendors.

Design and optimize hardware architecture for AI inference chips, collaborating with software teams to enhance performance and scalability.

This role is for recent graduates in various engineering functions. Responsibilities include adapting to a fast-paced environment and utilizing analytical skills.

The Physical Failure Analysis Engineer conducts analysis of manufacturing defects using various imaging tools and collaborates across departments to document and communicate findings.