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Sustain and improve plasma etch processes to meet safety, quality, cycle time, cost, and yield targets. Develop and qualify process recipes, analyze process and equipment data, drive root-cause investigations, execute experiments, implement corrective actions, manage process changes through change control, and collaborate with equipment, metrology, yield, and integration teams to support production.

Perform synthesis, place-and-route, STA and ECO implementation to achieve timing closure. Debug setup/hold violations, optimize designs for performance and area, develop constraints, run EDA tool flows across modes and corners, and collaborate with RTL, DFT, and signoff teams to ensure tapeout readiness.

This job involves leading engineering efforts related to compiler technology at NXP. Responsibilities include overseeing projects, collaborating with teams, and innovating solutions.

As a Technical Director - System Architect, you will drive the architecture of UHF RFID systems, collaborating on product requirements and system integration, while ensuring technical excellence throughout product development and customer interactions.

Lead the development of FPGA verification platforms, ensuring SoC functionality, coordinating with various teams, and reporting to customers while focusing on design quality and methodologies.

Lead SoC emulation programs and the Bangalore emulation team to develop, qualify, and deliver emulation models, enable platforms, optimize performance, drive automation, and collaborate across architecture, design, verification, firmware, and software teams to support pre-silicon validation.

Lead semiconductor process development and transfer projects from concept through qualification and release. Plan, monitor, and control schedules, costs, and technical deliverables; align cross-functional teams and external foundries; mitigate risks to yield, performance, and reliability; and improve project management practices.

Design and implement DfT features for complex analog/mixed-signal and digital IPs. Develop RTL in Verilog/SystemVerilog, insert and optimize scan chains, generate ATPG patterns, define verification plans, debug at chip-level DV, support silicon bring-up, and produce DfT architecture documentation.

Design, develop, and maintain integration solutions ensuring data accuracy and security, while leading junior engineers and optimizing processes.

The role involves designing and supporting complex electronic systems, overseeing PCB layout and ensuring cost-effective board designs for various applications.