As a DfT engineer, you will join a highly experienced team. Your key responsibilities will be:
1) Closely collaborate with Product Definer, Analog Design Lead, Digital Design Lead, Test Lead, Product Engineer, Quality Engineer, Validation Engineer – to identify the superset of requirements for Testability of the chip (Functional mode, Debug mode, ATPG).
2) Gain deep understanding on existing and innovative ways to insert DfT for complex analog and mixed-signal IPs, standard Macros (RAM, ROM, NVM, ADC, DAC) and complex digital logic.
3) High-quality of RTL design using Verilog and System-Verilog
4) Define Verification Plan for the implemented features and write tests, debug and get those passing at Chiptop level DV environment
5) Scan insertion, optimization, length balancing, P&R-aware rerouting of chains, Test-Point insertion, ATPG patterns generation, simulation and debug
6) Support Test Engineers during debug of patterns on new silicon, and on customer returns
7) Participate in Design & Test Review meetings and support the team for DfT
8) Generate comprehensive DfT Architecture & Design documentation and maintain it to match later updates
9) Troubleshoot and resolve issues related to DfT throughout the development lifecycle
10) Stay updated with the latest industry trends, tools, and methodologies in DfT design
Job Qualification:
- Master's degree (MSEE) with majority of courses relevant to Digital Design, RTL coding, DfT, Computer Architecture, Digital Verification.
- Minimum 3 years of experience in similar role of DfT, Digital Design & Architecture. Seeking 3-8 years total experience for this role
- Willing to relocate to Phoenix Metro area (Arizona) and minimum 3 days per week full-day presence in NXP's Chandler office
- Excellent on problem-solving, teamwork, planning, organizing, attention to detail and communication skills.
More information about NXP in the United States...
NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.
#LI-6692Skills Required
- Master's degree in Electrical Engineering (MSEE) with relevant courses in Digital Design, RTL coding, DfT, Computer Architecture, Digital Verification
- Minimum 3 years experience in DfT, Digital Design & Architecture (seeking 3-8 years total)
- Proficient RTL design using Verilog and SystemVerilog
- Hands-on DfT experience for analog and mixed-signal IPs and standard macros (RAM, ROM, NVM, ADC, DAC)
- Experience with scan insertion, optimization, length balancing, P&R-aware rerouting, and test-point insertion
- Experience generating ATPG patterns, simulation, and debug; supporting test engineers during silicon debug and customer returns
- Ability to define verification plans, write and debug tests in chip-level DV (Chiptop) environment
- Willingness to relocate to Phoenix Metro area and be in NXP's Chandler office minimum 3 days per week
- Strong problem-solving, teamwork, planning, organization, attention to detail, and communication skills
- Produce and maintain comprehensive DfT architecture and design documentation
What We Do
NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer and more sustainable world through innovation. As a world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has approximately 34,500 employees in more than 30 countries and posted revenue of $13.21 billion in 2022. Find out more at www.nxp.com. Privacy Policy: https://www.nxp.com/company/about-nxp/privacy-policy-for-social-media-pages:PRIVACY-POLICY-SOCIAL-MEDIA









