Top Tech Jobs & Startup Jobs

Design and develop reusable IP blocks for SoC integration: create micro-architecture, implement RTL (Verilog/SystemVerilog/VHDL), optimize for PPA, run lint/CDC/synthesis/STA checks, drive bug fixes, support sign-off, and collaborate with verification and cross-functional teams through silicon bring-up.

Lead and execute end-to-end IP/Subsystem verification for complex, multi-million-gate designs. Develop testplans and testbenches, run simulations and formal checks, drive verification methodology improvements, collaborate across design/DFT/mixed-signal teams, and support pre/post-silicon validation and emulation.

Lead physical implementation of IP/subsystem/IC from RTL synthesis to GDS. Perform floorplanning, routing, STA timing convergence, design ECOs, and physical verification to meet DRC/LVS, electromigration, and IR drop rules. Define physical design strategies per technology node and contribute to problem resolution and optimization.

Lead IP/subsystem roadmap and architecture, design complex IPs for edge and automotive (ASIL-D), drive development from concept to silicon-quality IP, ensure quality/process improvements, mentor global teams, and collaborate across SoC/system functions.

Design and execute verification plans for memory controllers, interconnects and infrastructural IPs. Build scalable SystemVerilog/UVM environments, drive functional and code coverage targets, manage regressions, debug RTL/testbench issues, and own end-to-end IP verification sign-off while collaborating with design teams.

Define and architect DC-DC systems integration in microcontroller products, oversee implementation, simulation, and support for design and architecture.

The Director, Global HR Business Partner engages with senior leaders to align people strategies with business objectives, influencing decisions through data and strategic insights while ensuring innovative talent management practices.

Lead export control and sanctions compliance for the AMEC region, driving strategy implementation, regulatory adherence, and operational efficiency while engaging stakeholders and optimizing processes.

Verify complex digital IPs (graphics pipelines, memory subsystems, interconnects) by developing/executing verification plans, building SystemVerilog/UVM environments, driving coverage metrics, managing regressions, debugging RTL/testbench issues, and owning end-to-end IP verification sign-off while collaborating with design and architecture teams.

Design, develop, and deliver automation solutions using Ansible, Python, and GitLab CI/CD to automate networks, storage, servers, virtualization, cloud, and OS platforms. Drive zero-downtime, self-service, and self-healing operations and participate in operational management of the Automation Platforms & Services.