Top Tech Jobs & Startup Jobs

Lead physical implementation of IP, subsystem or IC from RTL synthesis through GDS, including floorplanning, routing, timing closure (STA), design ECOs, and physical verification to meet DRC/LVS, electromigration, and IR drop rules. Define physical design strategy per technology node and solve complex physical-design issues.

Lead and execute innovation initiatives end-to-end, manage partnerships and startup scouting, enable governance and reporting, prepare business cases, analyze market and technology trends, track KPIs, and drive cross-functional alignment to scale proofs-of-concept.

Provide day-to-day administrative support including calendar management, travel arrangements, document archiving, basic reports and presentations, communications handling, procurement and expense support, and event coordination while collaborating with internal departments and following company procedures.

Entry-level DFT engineer supporting RTL-to-silicon SoC development: implement and verify DFT solutions (Scan, ATPG, MBIST, LBIST), assist RTL development, support synthesis and timing analysis, participate in silicon bring-up and post-silicon validation, and develop automation/scripting (including AI tools) to improve engineering efficiency.

Lead PERC rule development and methodology enablement for ESD, latch-up, power-domain, connectivity, and reliability verification. Develop, validate, and release Calibre PERC/LVS rule decks, translate signoff requirements into scalable checks, enable flows across IP/block/SoC, debug complex issues, build automation and regression suites, collaborate with design/CAD/technology teams, support tapeout and signoff, and mentor junior engineers.

The engineer is responsible for physical implementation from RTL to GDS, including design optimization, verification, and collaboration with teams. Requires 8+ years of experience.

Lead RTL and microarchitecture development for AI inference SoCs. Own IP/block-level design from specification through RTL, synthesis, timing closure, power optimization, integration, and silicon bring-up. Collaborate with verification, DFT, physical design, firmware, and architecture teams to ensure high-performance, low-power designs.

Support board-level hardware designs from concept through production: create schematics, select components, maintain BOMs, collaborate with PCB/layout and cross-functional teams, perform board bring-up, debugging, validation, and documentation, and support manufacturability and compliance testing.

Lead SoC and micro-architecture for AI inference accelerators, define compute/memory/interconnect subsystems, perform PPA trade-offs, collaborate with RTL, physical-design and software teams, build performance models and validate against RTL/emulation.

Define roadmap and product specifications for protocol bridges and connectivity hubs. Engage customers, perform competitive analysis, coordinate cross-functional teams to develop demos, reference designs, and documentation. Provide application support, technical training, and contribute to standards while overseeing development of demonstration boards and securing design-ins.