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Define and execute analog/RF/mixed-signal verification strategies and integration test frameworks to validate PDKs, tools, and methodologies across process nodes (28nm–5nm). Collaborate with AMS flow, PDK, IP teams and EDA vendors, perform qualitative/quantitative analyses, and leverage AI-driven automation to improve quality and productivity.

Architect system-level SoC platforms across product tiers: define architecture specs, hardware/software partitioning, KPIs, and IP requirements. Collaborate with cross-functional teams through design and productization, perform make-vs-buy and performance/power/area tradeoff analyses, and ensure compliance with automotive safety and mixed-criticality standards.

The AI Software Engineer will design, develop, and optimize infrastructure for the Discrete NPU Model Zoo, focusing on computer vision, generative AI, and LLM workloads. Responsibilities include developing performance workflows, benchmarking pipelines, and utilizing deep learning architectures.

Lead and mentor junior engineers in physical design, ensuring high-performance semiconductor IC delivery, managing floor planning, timing analysis, and verification tasks.

The Principal Engineer will lead the design and implementation of enterprise identity governance solutions, focusing on lifecycle management, access governance, and Zero Trust security, while mentoring other engineers.

This role involves architecting compiler subsystems, leading deployment strategies, optimizing performance, and mentoring engineers within AI solutions.

The Sales Operations Manager supports users on application incidents, manages revenue goal setting, evaluates billings, prepares presentations, and analyzes data to drive business insights.

The Functional Safety Architect defines and validates safety requirements for embedded systems, collaborates with teams, and ensures ISO compliance.

As a Junior Layout Engineer, you'll deliver analog layout blocks and floorplan activities, ensuring quality verification and documentation while collaborating with cross-functional teams.

Lead and mentor engineers in physical design methodology, perform power analysis, and ensure the timely delivery of semiconductor designs.