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Develop and plan features for new and existing configuration tools for automotive embedded systems. Build complex software solutions, collaborate with a global team within SAFe, engage with internal and external customers, and ensure tools simplify programming of NXP processors.

The Junior Layout Engineer will contribute to floorplan activities, design analog layout blocks, perform physical verifications, and support integration while ensuring quality and reliability.

The Industrial Engineer develops solutions for manufacturing processes, enhances operational efficiency, collaborates across teams, and implements Lean principles.

The role involves designing high performance digital logic and SoC integration, conducting IP integration reviews, and ensuring design quality through various signoffs.

Analyze wafer sort, final test, and inline process data to identify trends and root causes; develop predictive and diagnostic ML models, dashboards, and automated data pipelines; collaborate with cross-functional engineering teams and suppliers to deploy and sustain solutions that improve yield and product quality.

Lead STA efforts for SoC and block-level timing signoff: develop and maintain SDC constraints, perform MCMM timing analysis across PVT corners, debug setup/hold/transition/PBA violations, drive ECO-based closure, automate EDA flows, collaborate with architects/RTL/PD/DFT, and manage an STA engineering team.

Design and architect digital modules and microarchitecture for MCU/embedded processors. Develop synthesizable RTL (Verilog/SystemVerilog), perform IP integration, FPGA prototyping, timing/power/area analysis, and collaborate across verification, DFT, firmware, and validation teams while applying AI/ML-assisted design methodologies.

Act as the bridge between quality business processes and IT, focusing on product traceability. Gather requirements, design and implement IT solutions, perform analysis and testing, provide technical guidance, and support operations within Agile teams while collaborating with stakeholders and external partners.

Design and develop synthesizable RTL and microarchitecture for MCU/embedded processors, perform IP integration, FPGA prototyping and silicon bring-up, and analyze timing/power/area. Apply AI/ML-assisted methods to optimize PPA, collaborate with verification/DFT/firmware/validation teams, and support synthesis and static timing analysis.

Lead architecture, implementation, and UVM-based verification of Ethernet/networking IP and SoC products. Develop directed and random tests, debug failures, analyze coverage, collaborate with architects and designers, produce specification documentation, and continuously improve verification methodology and infrastructure.