Top Tech Jobs & Startup Jobs

Own end-to-end physical design for advanced SoCs, from RTL through GDSII and silicon delivery. Lead floorplanning, synthesis, place and route, CTS, routing, timing, power, physical verification, and signoff while meeting PPA targets. Drive methodology, automation, advanced-node implementation, team mentoring, cross-functional collaboration, EDA vendor engagement, post-silicon bring-up, yield improvement, and production ramp activities.

Architect and develop system management firmware for NXP i.MX SoCs and development boards. Port firmware to new hardware, integrate it across bootloader, trusted firmware, Linux, and MCU SDK components, and develop tests for coverage and performance. Collaborate with architecture, BSP, and support teams to debug and optimize customer systems. Produce documentation and support materials.

Leads STA and physical design timing closure for complex AI, edge, and automotive processor SoCs. Manages engineers, develops and verifies timing constraints, drives subsystem and full-chip closure, improves timing methodologies, and coordinates with architecture, RTL, DV, DFT, EDA, and global design teams. Requires expertise in advanced timing analysis, crosstalk, noise, OCV, clock behavior, jitter, IR drop, and SPICE analysis, along with technical leadership across multi-site teams.

Leads end-to-end SoC physical design from RTL through tapeout, including floorplanning, synthesis, place and route, timing, power, physical verification, and signoff. Manages global teams, execution schedules, cross-functional alignment, EDA vendor relationships, methodology improvements, advanced-node implementation, and post-silicon production support.

Provides administrative support for office operations, procurement, invoice processing, accounting coordination, business travel, meetings, visitors, events, office supplies, facilities, shipments, and logistics. The role also supports external service providers and process improvement initiatives. Fluency in Croatian and English, Microsoft Office proficiency, strong organization, problem-solving, attention to detail, and the ability to manage multiple priorities are required.

Leads static timing analysis for complex ASIC and SoC designs, including SDC constraint development, MCMM timing signoff, violation debugging, timing closure, ECO evaluation, and IP-level synthesis. Guides STA engineers, automates EDA implementation flows, and collaborates with RTL, physical design, DFT, architecture, and verification teams to achieve performance and tape-out goals.

Designs and validates custom high-speed IO circuits, including GPIO, DDR, SerDes, ESD protection, buffers, drivers, and termination circuits. Performs transistor-level simulations, signal integrity analysis, layout reviews, reliability checks, silicon bring-up, characterization, debugging, and production support. Collaborates with physical design, package, reliability, system, and product engineering teams while maintaining design and verification documentation.

Manage multi-site embedded software development teams delivering functional safety products for automotive microcontrollers. Drive the software development lifecycle, quality processes, planning, risk management, stakeholder communication, customer and marketing interactions, and audit support. The role leads engineers across Czech and international teams while ensuring high-quality delivery aligned with ISO 26262 functional safety requirements.

Prepare IFRS and local GAAP statutory financial statements, trial balances, management reports, audit documentation, and country reporting submissions. Coordinate statutory audits, collaborate on tax and treasury inputs, and identify automation and standardization opportunities across entities. The role requires a qualified accountant with strong accounting knowledge, Excel and SAP ERP proficiency, English communication skills, and the ability to meet tight deadlines.

The Verification Engineer will verify digital hardware architectures, create verification plans, develop verification strategies and tests for security hardware, and introduce verification methodologies.