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Supports senior field application engineers with customer schematic and layout reviews for optical modules and interconnect products. Assists with signal and power integrity simulations, product bring-up, performance testing, lab tuning, hardware/software debugging, customer issue resolution, and technical documentation. The internship provides hands-on exposure to PAM4 and coherent DSP technologies, optical communication systems, SerDes, and field application engineering workflows.

Supports customer optical-module firmware and software development, lab automation, module bring-up, TX/RX performance testing, hardware/software debugging, firmware flashing, register access, logging, compliance checks, and technical documentation. The intern works with senior field application engineers and customer teams on PAM4, coherent DSP, and optical technologies.

Own customer demand forecasting and revenue execution for major technology customers. Drive forecast accuracy, variance management, bookings, backlog, supply, allocation, logistics, and delivery issue resolution. Lead executive business reviews and translate customer demand signals into executable internal plans. Partner cross-functionally with Finance, Planning, Pricing, Legal, Supply Chain, and Sales while influencing teams without formal authority.

Lead the physical design organization and RTL-to-GDSII implementation of advanced SoCs. Responsibilities include methodology development, synthesis, floorplanning, power planning, place and route, clock tree synthesis, timing and signoff, physical verification, tapeout execution, team leadership, hiring, mentoring, resource planning, cross-functional alignment, and EDA tool deployment.

Lead physical design methodology and automation for next-generation processor and ASIC chips. Provide technical leadership across RTL-to-GDSII implementation, synthesis, floorplanning, place and route, clock tree synthesis, timing closure, power and signal integrity analysis. Collaborate globally with RTL, verification, CAD, and EDA vendors; evaluate tools, influence technical roadmaps, resolve complex implementation issues, and mentor engineers.

Lead physical design and methodology for complex processor and ASIC chips. Drive RTL-to-GDS implementation, multi-voltage place-and-route, static timing, physical verification, integration, and design closure. Collaborate with digital, RTL, and analog teams, while providing technical direction and mentoring. Develop Shell, Python, and Tcl automation scripts to improve design productivity and robustness.

Defines next-generation AI networking switch ASIC architectures for hyperscale cloud and AI workloads. Leads architectural decisions, performance modeling, simulation, trade-off analysis, standards development, and roadmap direction. Collaborates with silicon, software, systems, product, and customer teams; represents Marvell in standards bodies and strategic discussions; and mentors engineering teams.

Develop embedded firmware for DSP hardware, create test code, manage software development flows, and debug issues with HW/SW teams.

Provide L2/L3 deskside and remote support for Windows and macOS; manage onboarding, provisioning, MDM enrollment, hardware asset lifecycle, IMACs, and IT procurement. Operate and administer Zoom Rooms and enterprise AV hardware, perform preventive maintenance and AV troubleshooting, coordinate vendors, support events, and maintain AV runbooks and documentation.

Support Storage Business Unit FP&A by building financial models, forecasting, and variance analysis. Drive new product investment planning, month-end accounting controls, project tracking, costing, dashboards, and cross-functional reporting. Partner with business leaders, support planning cycles, and mentor junior team members to deliver actionable financial insights.